lec6_retiming

elec 7770 advanced vlsi design agrawal 21 algorithm

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Unformatted text preview: edges (vi, vj) for which wij ≥ 1. Create a level order for vertices such that an edge Create (vi, vj) requires order of vj to be higher than that of vi. vi. Traversing all nodes (v) in level order, compute ∆(v) ∆(v) = d(v), if v has no incoming edge ∆(v) = d(v) + max{∆(vi)}, for all incoming edges (vi, v)} i CP(G) = max{∆(vj), for all vertices j} j Spring 2014, Feb 10 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 22 Algorithm 1 Application 0 h 7 ∆=24 0 CP(G)=∆=24 g 1 ∆=3 Spring 2014, Feb 10 . . . Spring e 0 a 3 0 7 g 0 7 1 ∆=3 1 3 ∆=3 ELEC 7770: Advanced VLSI Design (Agrawal) d 0 0 b 3 ∆=10 e f 3 1 7 0 a c 3 1 ∆=17 0 0 b 3 1 3 7 f 0 0 0 7 0 0 1 h 0 c 1 3 d ∆=3 23 Algorithm 2: Retiming for Period = P Algorithm Initialize retiming variable, r(v) = 0, for all v. Repeat |V| – 1 times: Derive retiming graph. Run Algorithm 1 to determine ∆(v) for all v. For each v such that ∆(v) > P, set r(v) to r(v) + 1. Derive retiming graph and run Algorithm 1: If CP(G) > P, then no...
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This document was uploaded on 02/23/2014 for the course COMPUTER A 7770 at Auburn University.

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