spring elec 7770 advanced vlsi design agrawal 16

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Unformatted text preview: e 0→1 7 7 re= -2 rf= -1 0 0 0 f g 3 ra= -1 a 1 3 b 1→0 rb= -1 3 1 c rc= -2 3 d rd= -2 retiming vector = {-1,-1,-2,-2,-2,-1,0,0} Spring 2014, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 17 Retiming Theorem Given a network G(V, E, W) and a cycle time T, (r1, . . . ) is a Given feasible retiming if and only if: feasible 1. ri – rj ≤ wij for all edges (vi,vj) ε E ri wij for 2. ri – rj ≤ W(vi,vj) – 1 for all node-pairs vi, vj such that ri for D(vi,vj) > T Where, W(vi,vj): is the minimum weight for all paths between vi and vj D(vi,vj): is the maximum delay among all minimum weight paths between vi and vj Spring 2014, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 18 Proof of Condition 1 We assume that the original network is legal, i.e., all We edge weights are positive. edge For an arbitrary edge (vi,vj) ε E: For ri – rj ≤ wij or wij + rj – ri ≥ 0, means that after retiming the new ri weight wij’ = wij + rj – ri will be positive. Thus, condition 1 ensures the legality of retiming. ensures rj flip-flops ri flip-flops i wij flip-flops j Edge (i,j) Orig...
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This document was uploaded on 02/23/2014 for the course COMPUTER A 7770 at Auburn University.

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