spring elec 7770 advanced vlsi design agrawal 4

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Unformatted text preview: ELEC 7770: Advanced VLSI Design (Agrawal) 4 Example 3: Reduced Flip-Flops FF FF FF Spring 2014, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 5 Applications of Retiming Performance optimization Area optimization Power optimization Testability enhancement FPGA optimization Spring 2014, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 6 Fundamental Operation of Retiming A retiming move in a circuit is caused by moving retiming all of the memory elements at the input of a combinational block to all of its outputs, or vicecombinational versa. FF Combinational logic ≡ Combinational logic FF FF Spring 2014, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 7 A Correlator Circuit Adder delay = 7 + + = = = = a1 PO + a2 a3 a4 host PI Flip-flops Spring 2014, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) Comparator delay = 3 8 Graph Model f g 0 h 0 7 1 3 a 0 7 7 0 0 0 e 1 3 b 0 1 3 c 0 1 3 d Vertex vi: combinational, delay = d(vi), assumed unchanged by retiming d(host) = 0 Edge e(vi,vj): or eij, weight wij = number of flip-flops between vi and vj Spring 2014, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 9 Path Delay and Pat...
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