spring elec 7770 advanced vlsi design agrawal 9 path

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Unformatted text preview: h Weight A set of connected nodes specify a path. A path set does not traverse through the host node. does Path delay = ∑ d(vi) = combinational delay of path Path d(vi) Path weight = ∑ wij = clock delay of path Retiming of a node i is denoted by an integer ri IIt represents the number of registers moved across, t initially ri = 0 initially Register moved from output to input, ri → ri + 1 Register moved from input to output, ri → ri – 1 After retiming, edge weight wij’ = wij + rj – ri Spring 2014, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 10 Example of Node Retiming r1 = 0 r2 = 0 r3 = 0 r4 = 0 r5 = 0 r6 =0 3 3 3 3 3 3 ∑ d(vi) = 12, ∑ wij = 0 r1 = 0 r2 = -1 r3 = 0 r4 = 0 r5 = 1 r6 =0 3 3 3 3 3 3 ∑ d(vi) = 12, ∑ wij = 2 Spring 2014, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 11 Legal Retiming Retiming is legal if the retimed circuit has no Retiming negative weights. negative A llegally retimed circuit is functionally equivalent egally to the original circ...
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