For each v such that v p set rv to rv 1 derive

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Unformatted text preview: feasible retiming exists. Otherwise, CP(G) < P and the retimed graph is the Otherwise, required result. required Spring 2014, Feb 10 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 24 Algorithm 2 Application, P = 13 ∆=24 CP(G)=∆=24 h 0 7 g ∆=14 0 ∆=14 3 1 0 7 g ∆=14 Spring 2014, Feb 10 . . . Spring 1 7 1 ∆=3 3 1 7 e f 0 b1 ∆=3 c 3 1 a 3 ∆=3 1 ∆=7 0 0 b 3 1 0 e 0 ∆=3 ∆=10 7 f ∆=17 a 0 0 7 0 0 1 ∆=3 h 0 3 3 d ∆=10 0 c1 ∆=3 3 d ∆=3 ELEC 7770: Advanced VLSI Design (Agrawal) 25 Retimed Circuit for P = 13 0 h rh=0 1 7 rg=0 1 0 1→0 Critical path delay = 13 e 1 7 7 re= -2 rf= -1 0 0 0 f g 3 ra= -1 a 1 3 b 0 rb= -1 3 1 c rc= -2 3 d rd= -2 retiming vector = {-1,-1,-2,-2,-2,-1,0,0} Spring 2014, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 26 References Two papers by Leiserson ett al. (see slide 2). Two e G. De Micheli, Synthesis and Optimization of G. Digital Circuits, New York: McGraw-Hill, 1994. Digital N. Maheshwari and S. S. Sapatnekar, Timing N. Analysis and Optimization of Sequential Circuits , Analysis Boston: Springer, 1999. Boston: Spring 2014, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 27...
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