Thus condition 1 ensures the legality of retiming

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Unformatted text preview: inal flip-flops, wij Retimed flip-flops, wij’ = wij + rj – ri ≥ 0 Spring 2014, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 19 Proof of Condition 2 Given: d(vi) < T, for all i. Any retimed path whose combinational delay exceeds Any clock period, will have at least one flip-flop. clock The above is the requirement for correct operation. rj flip-flops ri flip-flops i Wij flip-flops j Path (i,j), D(i,j) > T Original weight, Wij Retimed weight, Wij’ = Wij + rj – ri ≥ 1 Spring 2014, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 20 Retiming Optimization Problem Retiming Given the initial retiming graph G(V, E, d, w) of a Given synchronous system and a required clock period P, find a feasible retiming transformation such that for the retimed graph G’ that CP(G’) ≤ P Solution: Algorithm 1 – Finds CP(G), critical path of G Algorithm 2 – Finds feasible retiming G → G’ Spring 2014, Feb 10 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 21 Algorithm 1: Critical Path Delay Algorithm Delete all...
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