lec6_retiming

# Negative a llegally retimed circuit is functionally

This preview shows page 1. Sign up to view the full content.

This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: uit – proof by Leiserson and Saxe (1991) Saxe Retiming is the most general method for Retiming changing the register count and position without knowing the functions of vertices. knowing Spring 2014, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 12 Example a c FF b x d 0 host c 1 0 x 0 Spring 2014, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 13 Example: Illegal Retiming 0 0 host c 0 0 0 1 0 x host 0 0 x 0 → –1 0 →1 Retiming vector = {0, 0, 0} b 1→0 0 → –1 0 a c Retiming vector = {0, 0, –1} c x FF d Spring 2014, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 14 Example: Legal Retiming 0 →1 0 0 host c 1 0 →1 x 0 0 0 host c 1→0 0 0 Retiming vector = {0, 0, 0} 0 x 0 0 Retiming vector = {0, 1, 0} FF a c b d Spring 2014, Feb 10 . . . Spring FF x ELEC 7770: Advanced VLSI Design (Agrawal) 15 Correlator Circuit f g 0 h rh=0 0 7 7 rf=0 rg=0 0 0 0 1 3 ra=0 a Critical path delay = 24 e 0 7 re=0 1 3 b rb=0 0 1 3 c rc=0 0 1 3 d rd=0 Initial retiming vector = {0,0,0,0,0,0,0,0} Spring 2014, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 16 Retimed Correlator Circuit 0 h rh=0 7 0→1 rg=0 0→1 0 1→0 Critical path delay = 13...
View Full Document

{[ snackBarMessage ]}

Ask a homework question - tutors are online