lec5_timing_verification

spring 82 6 11 2 1 8 3 5 11 2 5 6 11 1 8 3 6 5 8 2 8

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Unformatted text preview: 29 Example of a Transformation (2) a b c 2 1 2 d e 3 2 1 2 x Isolate and resynthesize 1 g y 2 Δ = 11 x = a’ + b’ + c’ + d’ + e’, Spring 2014, Feb 5 . . . Spring all inputs are symmetric. ELEC 7770: Advanced VLSI Design (Agrawal) 30 Example of a Transformation (3) d 3 b c 2 a e 1 2 1 2 2 1 2 x 1 y 2 g Δ=8 x = a’ + b’ + c’ + d’ + e’, Spring 2014, Feb 5 . . . Spring a and d are interchanged. ELEC 7770: Advanced VLSI Design (Agrawal) 31 32-bit Ripple-Carry Adder c0 a0 b0 FA0 a1 b1 sum0 sum1 FA1 a2 b2 FA2 sum2 a31 b31 Spring 2014, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) FA31 sum31 c31 32 One-bit Full-Adder Circuit ci ai bi Spring 2014, Feb 5 . . . Spring FAi XOR AND sumi XOR AND ELEC 7770: Advanced VLSI Design (Agrawal) OR Ci+1 33 Speeding Up the Adder b0-b15 cin a16-a31 b16-b31 0 a16-a31 b16-b31 1 Spring 2014, Feb 5 . . . Spring 16-bit ripple carry adder 16-bit ripple carry adder 16-bit ripple carry adder sum0-sum15 0 Multiplexer a0-a15 sum16-sum31, c31 1 This is a carry-select adder ELEC 7770: Advanced VLSI Design (Agrawal) 34...
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