spring elec 7770 advanced vlsi design agrawal 19

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Unformatted text preview: ELEC 7770: Advanced VLSI Design (Agrawal) 20 Speeding Up a Circuit Reducing the delay of a false path can increase circuit delay. 2 a 1 w a x 2 w u 2 2 v 2 y z u v x y z 0 1 2 3 4 5 6 7 time Spring 2014, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 21 Speeding Up a Circuit 2 a 1 False path w a x 2 w u 2 2 v 2 y z u v x y z 0 1 2 3 4 5 6 7 time Spring 2014, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 22 A Delay Optimization Algorithm REDUCE_DELAY (Circuit graph (V, E), ε) REDUCE_DELAY Repeat { Compute critical paths and critical delay Δ Compute Set output data ready time to Δ Set Compute slacks U = vertex subset with slack < ε vertex W = select vertices in U Apply transformation to vertices in W } until (no transformation can reduce Δ) until } G. De Micheli, Synthesis and Optimization of Digital G. Circuits, McGraw-Hill, 1994, p. 427. Circuits Spring 2014, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 23 Example: Critical Path Delay Compute data ready time from input to output a0 b c 0 2 2 1 3 0 d e 0 3 2 3 2 5 1 1 2 11 2 9 8 y 0 Critical p...
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