lec5_timing_verification

427 circuits spring 2014 feb 5 spring elec 7770

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ath delay, Δ = 11 Spring 2014, Feb 5 . . . Spring x 6 0 g 8 ELEC 7770: Advanced VLSI Design (Agrawal) 24 Example: Gate Slack Calculation Maximum time from input a0 b c 0 2 2 1 3 0 d e 0 3 2 3 2 5 1 1 2 11 2 9 8 y 0 Critical path delay, Δ = 11 Spring 2014, Feb 5 . . . Spring x 6 0 g 8 ELEC 7770: Advanced VLSI Design (Agrawal) 25 Example: Gate Slack Calculation Example: 2 a0 b c Maximum time to output 08 2 0 8 11 0 d e0 8 g 3 Spring 2014, Feb 5 . . . Spring 1 3 5 2 8 3 0 2 2 6 2 5 6 1 8 3 6 5 2 8 0 1 2 9 2 11 0 y 0 Critical path delay, Δ = 11 ELEC 7770: Advanced VLSI Design (Agrawal) x 26 Example: Gate Slack Calculation Example: 2 a0 b c Delay of longest path through gate 08 2 0 8 11 11 8 3 0 3 d e0 g 8 0 2 Spring 2014, Feb 5 . . . Spring 82 6 11 2 1 8 3 5 11 2 5 6 11 1 8 3 6 5 8 2 8 0 11 1 11 2 9 2 11 0 y 0 Critical path delay, Δ = 11 ELEC 7770: Advanced VLSI Design (Agrawal) x 27 Example: Gate Slack Calculation Example: 2 a0 b c Gate slack = Δ - Delay of longest path through gate 08 2 08 11 11 8 3 0 3 d e0 g 8 0 2 Spring 2014, Feb 5 . . . Spring 82 6 11 2 1 8 3 5 11 2 5 6 11 1 8 3 6 5 8 2 8 0 11 1 0 2 9 2 11 0 y 0 Critical path delay, Δ = 11 ELEC 7770: Advanced VLSI Design (Agrawal) x 28 Example of a Transformation (1) a b c 2 1 2 d e 3 2 1 2 x 1 g y 2 Δ = 11 x = a’ + b’ + c’ + d’ + e’ Spring 2014, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal)...
View Full Document

Ask a homework question - tutors are online