Lec5_timing_verification

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: is statically Longest unsensitizable. Such paths are often referred to, though not correctly (why?), as false paths. not as True path of length 3 a d1 1 e 2 1 1 b 0 Spring 2014, Feb 5 . . . Spring y 1 3 1 1 z f 1 ELEC 7770: Advanced VLSI Design (Agrawal) False path of length 4 7 An Example Statically unsensitizable (false) path. P. C. McGeer and R. K. Brayton, Integrating P. Functional and Temporal Domains in Logic Design, Springer, 1991. Design a False path of delay 3 e 1 0 1 d b c 1 1 1 0 g f 0 Spring 2014, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 8 Example (Cont.) Another statically unsensitizable false path. P. C. McGeer and R. K. Brayton, Integrating P. Functional and Temporal Domains in Logic Design, Springer, 1991. Design a 1 Two false paths of delay 3 e 1 0 1 d b c 1 1 0 g f 0 Spring 2014, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 9 Example (Cont.) Two paths are dynamically sensitizable and will affect the Two timing if both are together faulty. timing P. C. McGeer and R. K. Brayton, Integrating Functional P. and Temporal Domains in Logic Design, Spring...
View Full Document

This document was uploaded on 02/23/2014 for the course COMPUTER A 7770 at Auburn University.

Ask a homework question - tutors are online