elec 7770 advanced vlsi design agrawal 7 why do we

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Unformatted text preview: wal) 7 Why Do We Need Setup? Why SR-latch D Q CK=1 Latch open Q Legal inputs are 10 or 01 when Latch closes Spring 2014, Feb 21 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 8 Latch Inputs Latch tp 1 D 0 Ts Th time Tc.Q 1 CK 0 Tr time Tc.Q : Clock to Q delay Spring 2014, Feb 21 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 9 Master-Slave D-Flip-Flop Master-Slave Master latch D Slave latch Q Q CK Spring 2014, Feb 21 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 10 Master-Slave D-Flip-Flop Master-Slave Uses two level-sensitive clocked D-latches. Transfers data (D) with one clock period delay. Operation is edge-triggered: Operation edge-triggered Negative edge-triggered, CK = 1→0, Q = D (previous Negative slide) slide) Positive edge-triggered, CK = 0→1, Q = D Spring 2014, Feb 21 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 11 Negative-Edge Triggered D-Flip-Flop Negative-Edge Clock period, Tck Master open Slave closed CK Slave open Master closed Triggering clock edge Setup time, Ts Hold time, Th Clock-to-Q delay, Tc.Q D Data can change Data stable Data can change Time Spring 2014, Feb 21 . . ....
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