spring c 1 d 2 h 9 10 j 3 e 1 4 4 g 2 f 1

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 2 H 9, 10 j 3 E 1 4, 4 G 2 ∞ , -∞ ∞ , -∞ F 1 5, 5 ELEC 7770: Advanced VLSI Design (Agrawal) 6, 7 J 6, 8 1 k 23 Maximum Clock Frequency for Maximum Tolerance ±q/2 in Skew ±q/2 Linear program: Minimize Tck Subject to: For all flip-flop pairs (i,j), si + δ(i,j) ≥ sj + Thj + q si + Δ(i,j) ≤ sj + Tck – Tsj – q Where q is a constant si are variables, simin ≤ si Tck is a variable Spring 2014, Feb 21 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 24 Maximum Tolerance for Given Clock Maximum Frequency Frequency Linear program: Maximize q Subject to: For all flip-flop pairs (i,j), si + Tc.Qi + δ(i,j) ≥ sj + Thj + q si + Tc.Qi+ Δ(i,j) ≤ sj + Tck – Tsj – q Where Tck, Tc.Qi, Thj and Tsj are constants si are variables, simin ≤ si q is a variable Spring 2014, Feb 21 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 25 No solution because of zero slack. Increasing skew tolerance q Tradeoffs Increasing clock period Tck Spring 2014, Feb 21 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 26 Clock Skew Problem N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits , Springer, 1999. J. P. Fishburn, “Clock Skew Optimization,” IEEE J. Trans. Computers, vol. 39, no. 7, pp. 945-951, Trans. vol. July 1990. July Spring 2014, Feb 21 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 27...
View Full Document

Ask a homework question - tutors are online