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Unformatted text preview: ELEC 7770: Advanced VLSI Design (Agrawal) 12 Skews for Single-Cycle Paths FFi CKi Combinational Block Delay: δ(i,j) ≤ d(i,j) ≤ Δ(i,j) si FFj CKj sj skews, si and sj are delays from a common clock generator Spring 2014, Feb 21 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 13 Short-Path Constraint (Double-Clocking) Tck CKi si Not intended CKj intended Thj sj δ(i,j) Condition to avoid double clocking: si + Tc.Q + δ(i,j) ≥ sj + Thj Spring 2014, Feb 21 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 14 Long-Path Constraint (Zero-Clocking) Tck CKi si intended Not intended CKj sj Tsj Tc.Q+ Δ(i,j) Condition to avoid zero clocking: si + Tc.Q + Δ(i,j) ≤ sj + Tck – Tsj Spring 2014, Feb 21 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 15 Maximum Clock Frequency Linear program: Objective function, Minimize Tck Subject to constraints, for all flip-flop pairs (i,j), (1) si + Tc.Q + δ(i,j) ≥ sj + Thj short path (2) si + Tc.Q + Δ(i,j) ≤ sj + Tck – Tsj long...
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