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# Q ij sj thj short path 2 si tcq ij sj

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Unformatted text preview: path Spring 2014, Feb 21 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 16 Effects of Constraints Effects Short path: Independent of clock Minimum path delay: δ(i,j) ≥ sj – si – Tc.Q + Thj Minimum Long path: Minimum clock priod: Tck ≥ si – sj + Tc.Q + Δ(i,j) + Tsj Minimum Example: Shift register, assume δ(i,j) ≈ Δ(i,j) ≈ 0 Example: (i,j) si – sj ≥ Thj – Tc.Q > 0, si > sj for correct operation Tck ≥ si – sj + Tc.Q + Tsj, sj > si for maximum speed Clock routed opposite to data Spring 2014, Feb 21 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 17 Shift Register Example Delay ≈ 0 Delay = si Ci FFi sj Ri Cj Delay ≈ 0 FFj sk Rj FFk Ck Rk CK si + Tc.Q – sj ≥ Thj for correct operation Tck ≥ si – sj + Tc.Q + Tsj for correct operation Tck + si + Tc.Q – sj ≥ si – sj + Tc.Q + Tsj + Thj adding two inequalities Maximum clock speed: Tck = Tsj + Thj Spring 2014, Feb 21 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 18 Finding Clock Skews sk si CK FFi Ri Ci Rj FFj Cj Rk FFk Ck sj Use Elmore delay formula to calculate si, sj, sk. Spring 2014, Feb 21 . . . Spring ELEC 77...
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