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Spring ELEC 7770: Advanced VLSI Design (Agrawal) 4 Skews for Single-Cycle Paths FFi
δ(i,j) ≤ d(i,j) ≤ Δ(i,j) si FFj
CKj sj si and sj are arrival times of clock edges w.r.t. a reference time
Spring 2014, Feb 21 . . .
Spring ELEC 7770: Advanced VLSI Design (Agrawal) 5 Delay Latch or D-Latch
SR-latch D Q
Q Spring 2014, Feb 21 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 6 Setup and Hold Times of Latch
Setup Signals are synchronized with respect to clock (CK). Operation is level-sensitive:
Operation level-sensitive CK = 1 allows data (D) to pass through CK = 0 holds the value of Q, ignores data (D) Setup time is the interval before the clock transition
Setup during which data (D) should be stable (not change).
This will avoid any possible race condition.
Hold time is the interval after the clock transition during
which data should not change. This will avoid data from
latching Spring 2014, Feb 21 . . . ELEC 7770: Advanced VLSI Design (Agra...
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- Spring '14
- Trigraph, Clock rate, Clock signal, VLSI Design, Ri