spring 0 01 00 00 1 elec 5200 0016200 001

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Unformatted text preview: des instruction Datapath prepares for execution R and I types, reg 1→ A reg, reg 2 → B reg No control signals needed Branch type, compute branch address in ALUOut ALUSrcA ALUSrcB ALUOp Spring 2014, Feb 14 . . . Spring =0 = 11 = 00 select PC into ALU Instr. Bits 0-15 shift 2 into ALU ALU adds ELEC 5200-001/6200-001 Lecture 5 35 Cycle 3 of 5: Execute (EX) R type: execute function on reg A and reg B, result type: in ALUOut in Control signals used: ALUSrcA ALUsrcB ALUOp = = = 1 00 10 A reg into ALU B reg into ALU instr. Bits 0-5 control ALU I type, lw or sw: compute memory address in type, ALUOut ← A reg + sign extend IR[0-15] sign Control signals used: ALUSrcA ALUSrcB ALUOp Spring 2014, Feb 14 . . . Spring = = = 1 10 10 00 00 ELEC 5200-001/6200-001 Lecture 5 A reg into ALU Instr. Bits 0-15 into ALU ALU adds 36 Cycle 3 of 5: Execute (EX) I type, beq: subtract reg A and reg B, write ALUOut type, to PC to Control signals used: ALUSrcA = 1 ALUsrcB = 00 ALUOp = 01 If zero = 1, PCSource = 01 If zero = 1, PCwriteCond =1 Instruction complete, go to IF A reg into ALU B reg into ALU ALU subtracts ALUOut to PC write PC J type: write jump address to PC ← IR[0-25] shift 2 type: and four leading bits of PC and Control signals used: PCSource = 10 PCWrite = 1 write PC Instruction complete, go to IF Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 37 Cycle 4 of 5: Reg Write/Memory R type, write destination register from ALUOut Control signals used: RegDst = 1 Instr. Bits 11-15 specify reg. MemtoReg = 0 ALUOut into reg. RegWrite = 1 write register Instruction complete, go to IF I type, lw: read M[ALUOut] into MDR Control signals used: IorD MemRead = = 1 1 select ALUOut as mem adr. read memory to MDR I type, sw: write M[ALUOut] from B reg Control signals used: IorD = 1 select ALUOut as mem adr. MemWrite = 1 write memory Instruction complete, go to IF Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 38 Cycle 5 of 5: Reg Write I type, lw: write MDR to reg[IR(16-20)] Control signals used: RegDst = 0 iinstr. Bits 16-20 are write nstr. reg reg MemtoReg = 1 MDR to reg file write input RegWrite = 1 read memory to MDR Instruction complete, go to IF For an alternative method of designing datapath, see N. Tredennick, Microprocessor Logic Design, the Flowchart Method, Digital Press, 1987. Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 39 1-bit Control Signals Signal name Value = 0 Value =1 RegDst Write reg. # = bit 16-20 Write reg. # = bit 11-15 RegWrite No action Write reg. ← Write data ALUSrcA First ALU Operand ← PC First ALU Operand←Reg. A MemRead No action Mem.Data Output←M[Addr.] MemWrite No action M[Addr.]←Mem. Data Input MemtoReg Reg.File Write In←ALUOut Reg.File Write In←MDR IorD Mem. Addr. ← PC Mem. Addr. ← ALUOut IRWrite No action IR ← Mem.Data Output PCWrite No action PC is written PCWriteCond No action PC is written if zero(ALU)=1 zero(ALU) PCWriteCond PCWrite Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-00...
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This document was uploaded on 02/23/2014 for the course COMUPER AR 6200 at Auburn University.

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