spring elec 5200 0016200 001 lecture 5 17 datapath

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Unformatted text preview: 14 . . . Spring 28 Shift left 2 32 Address Instruction Memory 26 32 ELEC 5200-001/6200-001 Lecture 5 6 opcode (bits 26-31) to control Instruction word to control and registers 18 Instr. mem. 16-20 11-15 Combined Datapaths 0-15 Sign ext. Shift left 2 0 mux 1 1 mux 0 ALU zero MemtoReg MemWrite MemRead Data mem. 0 mux 1 PC 1 mux 0 21-25 ALU 26-31 Branch Reg. File opcode CONTROL RegDst Ad d 4 Jump Shift left 2 1 mux 0 0-25 ALU Cont. 0-5 Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 19 Control RegDst Jump Branch Instruction bits 26­31 opcode Control Logic MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite Instruction bits 0­5 funct. Spring 2014, Feb 14 . . . Spring 2 ALU Control ELEC 5200-001/6200-001 Lecture 5 to ALU 20 Control Logic: Truth Table Inputs: instr. opcode bits Outputs: control signals Instr Instr type type 31 30 29 28 27 26 R eg D s t R eg D s t Jump ALUSrc ALUSrc M em t oR eg M em t oR eg RegWr te RegWriite M em R ead M em R ead MemWr te MemWriite Branch Branch A LO O p 1 A LO O p 1 A LU O p 2 A LU O p 2 R 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 lw lw 1 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 sw sw 1 0 1 0 1 1 X 0 1 X 0 0 1 0 0 0 beq beq 0 0 0 1 0 0 X 0 0 X 0 0 0 1 0 1 j 0 0 0 0 1 0 X 1 X X 0 X 0 X X X Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 21 How Long Does It Take? Assume control logic is fast and does not Assume affect the critical timing. Major time delay components are ALU, memory read/write, and register read/write. and Arithmetic-type (R-type) Fetch (memory read) Register read ALU operation Register write Total Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 2ns 1ns 2ns 1ns 6ns 22 Time for lw and sw (I-Types) ALU (R-type) Load word (I-type) – Fetch (memory read) – Register read – ALU operation – Get data (mem. Read) – Register write – Total 6ns 2ns 1ns 2ns 2ns 1ns Store word (no register write) Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 8ns 7ns 23 Time for beq (I-Type) ALU (R-type) Load word (I-type) Store word (I-type) Branch on equal (I-type) – Fetch (memory read) – Register read – ALU operation 2ns 1ns 2ns 5ns – Total Spring 2014, Feb 14 . . . Spring 6ns 8ns 7ns ELEC 5200-001/6200-001 Lecture 5 24 Time for Jump (J-Type) ALU (R-type) Load word (I-type) Store word (I-type) Branch on equal (I-type) Jump (J-type) – Fetch (memory read) 2ns 2ns – Total Spring 2014, Feb 14 . . . Spring 6ns 8ns 7ns 5ns ELEC 5200-001/6200-001 Lecture 5 25 How Fast Can Clock Run? If every instruction is executed in one clock If cycle, then: cycle, – Clock period must be at least 8ns to perform Clock the longest instruction, i.e., lw. lw – This is a single cycle machine. – It is slower because many instructions take less It than 8ns but are still allowed that much time. than Method of speeding up: Use multicycle Method datapath. datapath. Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 26 A Single Cycle Example Delay of 1-bit full adder = 1ns Clock...
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This document was uploaded on 02/23/2014 for the course COMUPER AR 6200 at Auburn University.

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