lec5_datapath_control

spring fsm r opcode beq fsm b elec 5200 0016200 001

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Add Shift left 2 ALU control ALUOp = 00 47 State 1 (Opcode= sw)→FSM-M (CC3-4) CC4 MUX in1 control IRWrite CC4 in2 MemRead MemWrite=1 Spring 2014, Feb 14 . . . Spring RegDst=0 MemtoReg 0-15 Sign extend 0-5 ELEC 5200-001/6200-001 Lecture 5 4 CC3 ALU ALUSrcB=10 ALUSrcA=1 A Reg. 28-31 ALUOut Reg. Shift left 2 RegWrite B Reg. out 16-20 21-25 Register file Data 0-25 Mem. Data (MDR) IorD=1 Memory Addr. PC 26-31 to Control FSM Instr. reg. (IR) PCWrite et c. PCSource Add Shift left 2 ALU control ALUOp = 00 48 FSM-M (Memory Access) From state 1 Opcode = “lw” or “sw” Opcode Read Memory data Compute mem addrress ALUSrcA =1 ALUSrcB = 10 Opcode ALUOp = 00 = “lw” = “sw” MemRead = 1 IorD = 1 Write register RegWrite = 1 MemtoReg = 1 RegDst = 0 Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 Write memory MemWrite = 1 IorD = 1 To state 0 (Instr. Fetch) 49 State 1(Opcode=R-type)→FSM-R (CC3-4) MUX in1 control in2 MemRead MemWrite Spring 2014, Feb 14 . . . Spring IRWrite RegDst=0 4 CC4 MemtoReg=0 0-15 Sign extend 0-5 ELEC 5200-001/6200-001 Lecture 5 ALUOut Reg. ALU ALUSrcB=00 A Reg. CC3 28-31 ALUSrcA=1 11-15 Shift left 2 RegWrite B Reg. out 16-20 21-25 Register file Data 0-25 Mem. Data (MDR) IorD Memory Addr. PC 26-31 to Control FSM Instr. reg. (IR) PCWrite et c. PCSource “funct. code” Shift left 2 ALU control ALUOp = 10 50 FSM-R (R-type Instruction) From state 1 Opcode = R-type ALU operation ALUSrcA =1 ALUSrcB = 00 ALUOp = 10 Write register RegWrite = 1 MemtoReg = 0 RegDst = 1 Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 To state 0 (Instr. Fetch) 51 State 1 (Opcode = beq ) → FSM-B (CC3) MUX in1 control in2 MemRead MemWrite Spring 2014, Feb 14 . . . Spring IRWrite RegDst MemtoReg 0-15 Sign extend 0-5 ELEC 5200-001/6200-001 Lecture 5 4 ALUOut Reg. zero ALU ALUSrcB=00 CC3 28-31 ALUSrcA=1 11-15 A Reg. 16-20 PCSource 01 Shift left 2 RegWrite B Reg. out 0-25 Register file Data 21-25 Mem. Data (MDR) IorD Memory Addr. PC 26-31 to Control FSM Instr. reg. (IR) PCWrite etc.=1 If(zero) subtract Shift left 2 ALU control ALUOp = 01 52 Write PC on “zero” zero=1 PCWriteCond=1 PCWrite etc.=1 PCWrite PCWrite = 1, unconditionally write PC Cycle 1, fetch Cycle 3, jump Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 53 FSM-B (Branch) From state 1 Opcode = “beq” Write PC on branch condition ALUSrcA =1 ALUSrcB = 00 ALUOp = 01 PCWriteCond=1 PCSource=01 Branch condition: If A – B=0 zero = 1 To state 0 (Instr. Fetch) Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 54 State 1 (Opcode = j) → FSM-J (CC3) MUX in1 control in2 MemRead MemWrite Spring 2014, Feb 14 . . . Spring IRWrite 0-15 Sign extend 0-5 ELEC 5200-001/6200-001 Lecture 5 ALUOut Reg. zero ALU 28-31 ALUSrcB A Reg. RegWrite RegDst MemtoReg Shift left 2 ALUSrcA 11-15 PCSource 10 B Reg. out 16-20 21-25 Register file Data 0-25 Mem. Data (MDR) IorD Memory Addr. PC 26-31 to Control FSM Instr. reg. (IR) PCWrite et c. CC3 4 Shift left 2 ALU control ALUOp 55 Write PC zero PCWriteCond PCWrite=1 PCWrite etc.=1 PCWrite = 1, unconditionally write PC Cycle 1, fetch Cycle 3, jump Spring 2014,...
View Full Document

Ask a homework question - tutors are online