lec5_datapath_control

A memread no action memdata outputmaddr memwrite no

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Unformatted text preview: 1 Lecture 5 PCWrite etc. 40 2-bit Control Signals Signal name Value Action 00 Funct. field (0-5 bits of IR ) determines ALU operation Second input of ALU ← B reg. 01 Second input of ALU ← 4 (constant) 10 Second input of ALU ← 0-15 bits of IR sign ext. to 32b 11 Second input of ALU ← 0-15 bits of IR sign ext. and Second left shift 2 bits left 00 ALU output (PC +4) sent to PC 01 ALUOut (branch target addr.) sent to PC 10 PCSource ALU performs subtract 00 ALUSrcB 01 10 ALUOp ALU performs add Jump address IR[0-25] shifted left 2 bits, Jump concatenated with PC+4[28-31], sent to PC concatenated Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 41 Control: Finite State Machine Start State 0 Clock cycle 1 Instruction fetch State 1 Clock cycle 2 Instruction decode and register fetch FSM-M Clock cycles 3­5 Memory access instr. Spring 2014, Feb 14 . . . Spring FSM-R R-type instr. FSM-B Branch instr. ELEC 5200-001/6200-001 Lecture 5 FSM-J Jump instr. 42 State 0: Instruction Fetch (CC1) MUX in1 control in2 MemRead = 1 MemWrite Spring 2014, Feb 14 . . . Spring IRWrite =1 RegDst MemtoReg 0-15 Shift left 2 Sign extend 0-5 ELEC 5200-001/6200-001 Lecture 5 4 ALUOut Reg. ALU ALUSrcB=01 28-31 ALUSrcA=0 A Reg. RegWrite B Reg. out 16-20 21-25 Register file Data 0-25 Mem. Data (MDR) IorD=0 Memory Addr. PC 26-31 to Control FSM Instr. reg. (IR) PCWrite etc.=1 PCSource=00 Add Shift left 2 ALU control ALUOp =00 43 State 0 Control FSM Outputs Start State0 Instruction fetch MemRead =1 ALUSrcA = 0 IorD = 0 IRWrite = 1 ALUSrcB = 01 ALUOp = 00 PCWrite = 1 PCSource = 00 Spring 2014, Feb 14 . . . Spring State 1 Instruction decode/ Register fetch/ Branch addr. ELEC 5200-001/6200-001 Lecture 5 Outputs? 44 State 1: Instr. Decode/Reg. Fetch/ State Branch Address (CC2) Branch MUX in1 control in2 MemRead MemWrite Spring 2014, Feb 14 . . . Spring IRWrite RegDst MemtoReg 0-15 Shift left 2 Sign extend 0-5 ELEC 5200-001/6200-001 Lecture 5 4 ALUOut Reg. ALU ALUSrcB=11 28-31 ALUSrcA=0 A Reg. RegWrite B Reg. out 16-20 21-25 Register file Data 0-25 Mem. Data (MDR) IorD Memory Addr. PC 26-31 to Control FSM Instr. reg. (IR) PCWrite et c. PCSource Add Shift left 2 ALU control ALUOp = 00 45 State 1 Control FSM Outputs Start State0 Instruction fetch MemRead =1 (IF) ALUSrcA = 0 IorD = 0 IRWrite = 1 ALUSrcB = 01 ALUOp = 00 PCWrite = 1 PCSource = 00 State 1 Instruction decode (ID) / Register fetch / Branch addr. ALUSrcA = 0 ALUSrcB = 11 ALUOp = 00 = de pco sw de = O lw, pco pe O R-ty FSM-M Spring 2014, Feb 14 . . . Spring FSM-R Opcode = BEQ FSM-B ELEC 5200-001/6200-001 Lecture 5 Opcode = J-type FSM-J 46 State 1 (Opcode = lw) → FSM-M (CC3-5) PCSource MUX in1 control in2 MemRead=1 MemWrite Spring 2014, Feb 14 . . . Spring IRWrite 4 RegDst=0 MemtoReg=1 0-15 Sign extend 0-5 ELEC 5200-001/6200-001 Lecture 5 CC3 ALU ALUSrcB=10 ALUSrcA=1 A Reg. 28-31 ALUOut Reg. CC5 B Reg. out 16-20 Shift left 2 RegWrite=1 21-25 Register file Data 0-25 Mem. Data (MDR) IorD=1 Memory Addr. PC 26-31 to Control FSM Instr. reg. (IR) PCWrite et c. CC4...
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