Fetch spring 2014 feb 14 spring elec 5200 0016200 001

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Unformatted text preview: Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 56 FSM-J (Jump) From state 1 Opcode = “jump” Write jump addr. In PC PCWrite=1 PCSource=10 To state 0 (Instr. Fetch) Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 57 Control FSM Start State 0 1 Instr. fetch/ adv. PC 3 w rs o lw 2 Read memory data Compute memory addr. lw Instr. decode/reg. fetch/branch R addr. B ALU operation 6 8 sw 4 5 Write register Spring 2014, Feb 14 . . . Spring J Write PC on branch condition Write jump addr. to PC 9 7 Write memory data Write register ELEC 5200-001/6200-001 Lecture 5 58 Control FSM (Controller) 6 inputs (opcode) 16 control outputs Combinational logic Present state Next state Reset Clock FF FF FF FF Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 59 Designing the Control FSM Encode states; need 4 bits for 10 states, e.g., – State 0 is 0000, state 1 is 0001, and so on. Write a truth table for combinational logic: Opcode 000000 .... Present state 0000 .... Control signals 0001000110000100 .... Next state 0001 .... Synthesize a logic circuit from the truth table. Connect four flip-flops between the next state outputs and Connect present state inputs. present Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 60 Block Diagram of a Processor MemWrite Reset Clock Mem. Addr. Datapath (PC, register file, registers, ALU) Mem. write data Mem. data out Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 61 ALUOp 3-bits PCWriteCond PCWrite IRWrite IorD MemtoReg RegWrite ALUSrcB 2-bits PCSource 2-bits RegDst ALUSrcA Overflow Opcode 6-bits zero ALU control funct. [0,5] ALUOp 2-bits Controller (Control FSM) MemRead Exceptions or Interrupts Conditions under which the processor may Conditions produce incorrect result or may “hang”. produce – – – Illegal or undefined opcode. Arithmetic overflow, divide by zero, etc. Out of bounds memory address. EPC: 32-bit register holds the affected EPC: instruction address. instruction Cause: 32-bit register holds an encoded Cause: exception type. For example, exception – 0 for undefined instruction – 1 for arithmetic overflow Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 62 MUX in1 0 control in2 1 Cause 32-bit register 4 EPCWrite=1 ALU ALUSrcB=01 ALUSrcA=0 Instr. reg. (IR) 26-31 to Control FSM CauseWrite=1 out PCSource 11 8000 0180(hex) PC PCWrite etc.=1 Implementing Exceptions EPC Overflow to Control FSM Subtract ALU control Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 ALUOp =01 63 How Long Does It Take? Again Assume control logic is fast and does not Assume affect the critical timing. Major time components are ALU, memory read/write, and register read/write. and Time for hardware operations, suppose Memory read or write Register read ALU operation Register write Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 2ns 1ns 2ns 1ns 64 Single-Cycle Datapath R-type Load word (I-type) Store word (I-type) Branch on equal (I-type) Jump (J-type) Clock cycle time = Clock Each in...
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This document was uploaded on 02/23/2014 for the course COMUPER AR 6200 at Auburn University.

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