It is slower because many instructions take less it

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Unformatted text preview: period ≥ 32ns a31 . . . a2 a1 a0 1-b full adder 1-b full adder b31 . . . b2 b1 b0 1-b full adder s31 . . . s2 s1 s0 1-b full adder 0 Spring 2014, Feb 14 . . . Spring c32 Time of adding words ~ 32ns Time of adding bytes ~ 32ns ELEC 5200-001/6200-001 Lecture 5 27 a31 . . . a2 a1 a0 b31 . . . b2 b1 b0 Spring 2014, Feb 14 . . . Spring Delay of 1-bit full adder = 1ns Clock period ≥ 1ns Time of adding words ~ 32ns Time of adding bytes ~ 8ns 1-b full adder c32 FF Initialize to 0 ELEC 5200-001/6200-001 Lecture 5 s31 . . . s2 s1 s0 S h i ft S h i ft S h i ft A Multicycle Implementation 28 Instr. mem. 16-20 Single-cycle Datapaths 0-15 11-15 Sign ext. Shift left 2 0 mux 1 1 mux 0 ALU zero MemtoReg MemWrite MemRead Data mem. 0 mux 1 PC 1 mux 0 21-25 ALU 26-31 Branch Reg. File opcode CONTROL RegDst Ad d 4 Jump Shift left 2 1 mux 0 0-25 ALU Cont. 0-5 Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 29 ALUOut Reg. 4 ALU A Reg. B Reg. Register file Mem. Data (MDR) Data Instr. reg. (IR) Addr. Memory PC Multicycle Datapath One-cycle data transfer paths (need registers to hold data) Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 30 Multicycle Datapath Requirements Only one ALU, since it can be reused. Single memory for instructions and data. Five registers added: – Instruction register (IR) – Memory data register (MDR) – Three ALU registers, A and B for inputs and Three ALUOut for output ALUOut Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 31 MUX in1 control in2 MemRead MemWrite Spring 2014, Feb 14 . . . Spring IRWrite RegDst MemtoReg 0-15 Sign extend 0-5 ELEC 5200-001/6200-001 Lecture 5 ALUOut Reg. ALU ALUSrcB 28-31 ALUSrcA A Reg. 1 1 -1 5 16-20 PCSource Shift left 2 RegWrite B Reg. out 21-25 Register file Data 0-25 Mem. Data (MDR) IorD Memory Addr. PC 26-31 to Control FSM Instr. reg. (IR) PCWrite et c. Multicycle Datapath 4 Shift left 2 ALU control ALUOp 32 3 to 5 Cycles for an Instruction Step R-type (4 cycles) Mem. Ref. (4 or 5 cycles) Branch type (3 cycles) J-type (3 cycles) Instruction fetch IR ← Memory[PC]; PC ← PC+4 Instr. decode/ Instr. Reg. fetch Reg. A ← Reg(IR[21-25]); B ← Reg(IR[16-20]) ALUOut ← PC + (sign extend IR[0-15]) << 2 Execution, Execution, addr. Comp., branch & jump completion completion Mem. Access Mem. or R-type completion completion ALUOut ← A op B Reg(IR[1115]) ← 15]) ALUOut ALUOut Memory read Memory completion completion Spring 2014, Feb 14 . . . Spring ALUOut ← A+sign extend (IR[0-15]) If (A= =B) then then PC←ALUOut PC←PC[2831] || (IR[0-25]<<2) MDR←M[ALUout] MDR←M[ALUout] or M[ALUOut]←B or Reg(IR[16-20]) ← Reg(IR[16-20]) MDR MDR ELEC 5200-001/6200-001 Lecture 5 33 Cycle 1 of 5: Instruction Fetch (IF) Read instruction into IR, M[PC] → IR Read IR Control signals used: IorD MemRead IRWrite = = = 0 1 1 select PC read memory write IR Increment PC, PC + 4 → PC Control signals used: ALUSrcA ALUSrcB ALUOp PCSource PCWrite Spring 2014, Feb 14 . . . Spring = = = = = 0 01 00 00 1 ELEC 5200-001/6200-001 Lecture 5 select PC into ALU select constant 4 ALU adds select ALU output write PC 34 Cycle 2 of 5: Instruction Decode (ID) 31-26 25-21 20-16 15-11 10-6 5-0 R opcode | reg 1 | reg 2 | reg 3 | shamt | fncode I opcode | reg 1 | reg 2 | word address increment J opcode | word address jump Control unit deco...
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This document was uploaded on 02/23/2014 for the course COMUPER AR 6200 at Auburn University.

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