Generates spring 2014 feb 14 spring elec 5200 0016200

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Unformatted text preview: 200-001/6200-001 Lecture 5 10 Datapath for R-Type Instruction 01000 10010 10001 000000 10001 10010 01000 00000 100000 Operation opcode $s1 $s2 $t0 function (add) opcode select from control (add) 5 $s1 Read 3 32 register zero numbers 5 $s2 32 Registers ALU result (reg. file) 32 overflow Write reg. 5 $t0 number Write data 32 RegWrite from control activated Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 11 Load and Store Instructions I-type instructions lw $t0, 1200 ($t1) lw # incr. in bytes 100011 01001 01000 0000 0100 1011 0000 0000 opcode $t1 sw sw $t0 $t0, 1200 ($t1) 1200 # incr. in bytes 101011 01001 01000 0000 0100 1011 0000 0000 opcode $t1 Spring 2014, Feb 14 . . . Spring $t0 ELEC 5200-001/6200-001 Lecture 5 1200 12 Datapath for lw Instruction Read register numbers 01001 100011 01001 01000 0000 0100 1011 0000 100011 0000 opcode $t1 $t0 1200 opcode 1200 5 $t1 3 32 01000 5 Operation select from control (add) result ALU Addr. Data memory overflow $t0 Write data Write data 0000 0100 1011 0000 Read data zero 5 32 Registers (reg. file) Write reg. number MemWrite 32 32 RegWrite from control activated 16 Spring 2014, Feb 14 . . . Spring MemRead activated Sign extend mem. data to $t0 ELEC 5200-001/6200-001 Lecture 5 13 Datapath for sw Instruction 01001 Read register numbers 5 01000 101011 01001 01000 0000 0100 1011 0000 101011 0000 opcode $t1 $t0 1200 opcode 1200 5 Write reg. number $t1 3 32 Operation select from control (add) Read data zero $t0 result ALU 32 Registers (reg. file) Addr. Data memory overflow 5 32 Write data 0000 0100 1011 0000 MemWrite activated $t0 data to mem. 32 Write data 32 RegWrite from control 16 Spring 2014, Feb 14 . . . Spring Sign extend ELEC 5200-001/6200-001 Lecture 5 MemRead 14 Branch Instruction (I-Type) beq beq $s1, $s2, 25 # iif $s1 = $s2, f advance PC through instructions instructions 25 16-bits 16-bits 000100 10001 10010 0000 0000 0001 1001 0000 opcode $s1 $s2 25 25 Note: Can branch within ± 215 words from the current instruction address in PC. Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 15 Datapath for beq Instruction 10001 Read register numbers 5 10010 16-bits 16-bits 000100 10001 10010 0000 0000 0001 1001 0000 opcode $s1 $s2 25 5 Write reg. number Operation select from control (subtract) $s1 32 3 $s2 32 Registers zero (reg. file) ALU 5 32 result To branch control logic overflow Write data 0000 00 00 0001 1001 32 16 Sign extend Spring 2014, Feb 14 . . . Spring RegWrite from control 32 PC+4 From instruction 32 fetch datapath Shift left 2 Add Branch target 32 32 ELEC 5200-001/6200-001 Lecture 5 16 J-Type Instruction j 2500 # jump to instruction 2,500 26-bits 26-bits 000010 0000 0000 0000 0010 0111 0001 00 000010 0000 opcode 2,500 opcode 2,500 32-bit jump address 0000 0000 0000 0000 0010 0111 0001 0000 bits 28-31 from PC+4 Spring 2014, Feb 14 . . . Spring ELEC 5200-001/6200-001 Lecture 5 17 Datapath for Jump Instruction Branch 4 Add Branch addr. 32 PC+4 Jump 1 mux 0 32 32 0 mux 1 4 32 PC Spring 2014, Feb...
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This document was uploaded on 02/23/2014 for the course COMUPER AR 6200 at Auburn University.

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