spring elec 5200 0016200 001 lecture 3 29 policy of

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Unformatted text preview: ode. pseudoinstructions Spring 2014, Jan 24 . . . Spring ELEC 5200-001/6200-001 Lecture 3 29 Policy of Register Usage Policy (Conventions) (Conventions) Name Register number $zero 0 $v0-$v1 2-3 $a0-$a3 4-7 $t0-$t7 8-15 $s0-$s7 16-23 $t8-$t9 24-25 $gp 28 $sp 29 $fp 30 $ra 31 Usage the constant value 0 values for results and expression evaluation arguments temporaries saved more temporaries global pointer stack pointer frame pointer return address Register 1 ($at) reserved for assembler, 26-27 for operating system 2004 © Morgan Kaufman Publishers Spring 2014, Jan 24 . . . Spring ELEC 5200-001/6200-001 Lecture 3 30 Constants Small constants are used quite frequently (50% of operands) Small e.g., A = A + 5; 5; B = B + 1; C = C – 18; Solutions? Why not? – put 'typical constants' in memory and load them. put – create hard-wired registers (like $zero) for constants like one. MIPS Instructions: addi $29, $29, 4 slti $8, $18, 10 andi $29, $29, 6 ori $29, $29, 4 Design Principle: Make the common case fast. Design Which format? Which 2004 © Morgan Kaufman Publishers Spring 2014, Jan 24 . . . Spring ELEC 5200-001/6200-001 Lecture 3 31 How About Larger Constants? We'd like to be able to load a 32 bit constant into a register Must use two instructions, new "load upper immediate" instruction lui $t0, 1010101010101010 1010101010101010 filled with zeros 0000000000000000 Then must get the lower order bits right, i.e., ori $t0, $t0, 1010101010101010 1010101010101010 0000000000000000 1010101010101010 1010101010101010 ori 0000000000000000 1010101010101010 2004 © Morgan Kaufman Publishers Spring 2014, Jan 24 . . . Spring ELEC 5200-001/6200-001 Lecture 3 32 Assembly Language vs. Assembly Machine Language Machine Assembly provides convenient symbolic representation much easier than writing down numbers e.g., destination first Machine language is the underlying reality e.g., destination is no longer first Assembly can provide 'pseudoinstructions' e.g., “move $t0, $t1” exists only in Assembly e.g., implemented using “add $t0, $t1, $zero” When considering performance you should count real instructions and clock cycles instructions 2004 © Morgan Kaufman Publishers Spring 2014, Jan 24 . . . Spring ELEC 5200-001/6200-001 Lecture 3 33 Overview of MIPS simple instructions, all 32 bits wide very structured, no unnecessary baggage only three instruction formats R op rs rt rd I op rs rt 16 bit address J op shamt funct 26 bit address rely on compiler to achieve performance 2004 © Morgan Kaufman Publishers Spring 2014, Jan 24 . . . Spring ELEC 5200-001/6200-001 Lecture 3 34 Addresses in Branches and Jumps Instructions: bne $t4, $t5, Label Next instruction is at Label Next if $t4 ≠ $t5 if beq $t4, $t5, Label Next instruction is at Label Next if $t4 = $t5 if $t4 Next instruction is at Label j Label Formats: Formats: I op J op rs rt 16 bit rel. address 26 bit absolute address 2004 © Morgan Kaufman Publishers Spring 2014, Jan 24 . . . Spring ELEC 5200-001/6200-001 Lecture 3 35 Addresses in Branches Instructions: bne $t4,$t5,Label beq $t4,$t5,Label Formats: Next instruction is at Label if $t4 ≠ $t5 Next $t5 Next instruction is at Label if $t4 = $t5 – 215 to 215 – 1 ~ ±32 Kwords ±32 op op rs rt 16 bit address 26 bit address Relative addressing 226 = 64 Mwords – with respect to PC (program counter) – most branches are local (principle of locality) Jump instruction just uses high order bits of PC Jump – address boundaries of 256 M...
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This document was uploaded on 02/23/2014 for the course COMUPER AR 6200 at Auburn University.

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