Elec 5200 0016200 001 lecture 3 42 summary mips

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Unformatted text preview: EC 5200-001/6200-001 Lecture 3 42 Summary: MIPS Instructions MIPS assembly language Category add Example add $s1, $s2, $s3 Meaning $s1 = $s2 + $s3 Three operands; data in registers subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; data in registers addi $s1, $s2, 100 lw $s1, 100($s2) sw $s1, 100($s2) lb $s1, 100($s2) sb $s1, 100($s2) lui $s1, 100 $s1 = $s2 + 100 Used to add constants $s1 = Memory[$s2 + 1 00]Word from memory to register Memory[$s2 + 100] = $s1 Word from register to memory $s1 = Memory[$s2 + 1 00]Byte from memory to register Memory[$s2 + 100] = $s1 Byte from register to memory $s1 = 100 * 2 16 Loads constant in upper 16 bits beq $s1, $s2, 25 if ( $s1 == $s2) go to PC + 4 + 100 Equal test; PC-relative branch branch on not equal bne $s1, $s2, 25 if ( $s1 != $s2) go to PC + 4 + 100 Not equal test; PC-relative set on less than slt $s1, $s2, $s3 if ( $s2 < $s3) $ s1 = 1; else $ s1 = 0 Compare less than; for beq, bne set less than immediate Arithmetic Instruction slti jump jump register jump and link j jr jal add immediate load w ord store w ord Data transfer load byte store byte load upper immediate branch on equal Conditional branch Unconditional jump Spring 2014, Jan 24 . . . Spring $s1, $s2, 100 if ($s2 < 100) $ s1 = 1; Comments Compare less than constant else $ s1 = 0 2500 $ra 2500 go to 10000 Jump to target address $ra go to For sw itch, procedure return $ra = PC + 4; go to 10000 For procedure call ELEC 5200-001/6200-001 Lecture 3 43 Addressing Modes Example 1. Immedi at e addressi ng addi add op rs rt Im mediate 2. Register addr essing op rs rt rd ... funct Reg isters Register 3. Base addr essing lw, sw op rs rt + Regist er beq, bne Me mo r y Addr ess Byte Halfw or d Word 4. PC-relati ve addressing op rs rt Me mo r y Addr ess + PC Word 5. Pse udodir ect addr essing j op Add ress Me mo r y Word PC 2004 © Morgan Kaufman Publishers Spring 2014, Jan 24 . . . Spring ELEC 5200-001/6200-001 Lecture 3 44 Alternative Architectures Design alternative: – provide more powerful operations – goal is to reduce number of instructions executed – danger is a slower cycle time and/or a higher CPI –“The path toward operation complexity is thus fraught with peril. To avoid these problems, designers have moved toward simpler instructions” Let’s look (briefly) at IA-32 2004 © Morgan Kaufman Publishers Spring 2014, Jan 24 . . . Spring ELEC 5200-001/6200-001 Lecture 3 45 1978: 1980: 1982: IA–32 (a.k.a. x86) The Intel 8086 is announced (16 bit architecture) The 8087 floating point coprocessor is added The 80286 increases address space to 24 bits, The +instructions +instructions 1985: The 80386 extends to 32 bits, new addressing modes 1989-1995: The 80486, Pentium, Pentium Pro add a few instructions (mostly designed for higher performance) 1997: 57 new “MMX” instructions are added, Pentium II 1997: 57 1999: The Pentium III added another 70 instructions (SSE – 1999: streaming SIMD extensions) streaming 2001: Another 144 instructions (SSE2) 2001: Another 2003: AMD extends the architecture to increase address space to 2003: 64 bits, widens all registers to 64 bits and makes other changes (AMD64) changes 2004: Intel capitulates and embraces AMD64 (calls it EM64T) and 2004: adds more media extensions adds “This history illustrates the impact of the “golden handcuffs” of compatibility: “adding new features as someone might add clothing to a packed bag” “an architecture that is difficult to explai...
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This document was uploaded on 02/23/2014 for the course COMUPER AR 6200 at Auburn University.

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