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Unformatted text preview: hapter 5. ARM (RISC)
D. Seal, ARM Architecture Reference Manual, Second Edition,
Addison-Wesley Professional, 2000.
Addison-Wesley SPARC (Scalable Processor Architecture)
V. C. Hamacher, Z. G. Vranesic and S. G. Zaky, Computer
Organization, Fourth Edition, New York: McGraw-Hill, 1996.
Organization, Spring 2014, Jan 24 . . .
Spring ELEC 5200-001/6200-001 Lecture 3 54 P×T
T P Av. execution time per instruction (T) Program size in machine instructions (P) Instruction Complexity
Instruction Increasing instruction complexity
Spring 2014, Jan 24 . . . ELEC 5200-001/6200-001 Lecture 3 55 URISC: The Other Extreme
Instruction set has a single instruction:
label: urisc dest, src1, target Subtract operand 1 from operand 2, replace operand 2 with
the result, and jump to target address if the result is
See, B. Parhami, Computer Architecture, from
Microprocessors to Supercomputers, New York: Oxford,
2005, pp. 151-153.
Spring 2014, Jan 24 . . . ELEC 5200-001/6200-001 Lecture 3 56 Summary
Instruction complexity is only one variable
– llower instruction count vs. higher CPI / lower clock
rate – we will see performance measures later
– simplicity favors regularity
– smaller is faster
– good design demands compromise
– make the common case fast
Instruction set architecture
– a very important abstraction indeed!
2004 © Morgan Kaufman Publishers Spring 2014, Jan 24 . . .
Spring ELEC 5200-001/6200-001 Lecture 3 57...
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This document was uploaded on 02/23/2014 for the course COMUPER AR 6200 at Auburn University.
- Spring '14