Architecture that is difficult to explain and

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Unformatted text preview: n and impossible to love” 2004 © Morgan Kaufman Publishers Spring 2014, Jan 24 . . . Spring ELEC 5200-001/6200-001 Lecture 3 46 IA-32 Overview Complexity: – Instructions from 1 to 17 bytes long – one operand must act as both a source and destination – one operand can come from memory – complex addressing modes e.g., “base or scaled index with 8 or 32 bit displacement” Saving grace: – the most frequently used instructions are not too difficult to build – compilers avoid the portions of the architecture that are slow “what the x86 lacks in style is made up in quantity, what making it beautiful from the right perspective” making 2004 © Morgan Kaufman Publishers Spring 2014, Jan 24 . . . Spring ELEC 5200-001/6200-001 Lecture 3 47 IA-32 Registers Registers in the 32-bit subset that originated with 80386 Name U se 31 0 EAX GPR 0 ECX GPR 1 EDX GPR 2 EBX GPR 3 ESP GPR 4 EBP GPR 5 ESI GPR 6 EDI GPR 7 CS Data segment pointer 1 FS Data segment pointer 2 GS Spring 2014, Jan 24 . . . Spring Data segment pointer 0 ES EFLAGS Stack segment pointer (top of stack) DS EIP Code segment pointer SS Eight general purpose registers Data segment pointer 3 Instruction pointer (PC) Condition codes ELEC 5200-001/6200-001 Lecture 3 2004 © Morgan Kaufman Publishers 48 IA-32 Register Restrictions Fourteen major registers. Eight 32-bit general purpose registers. ESP or EBP cannot contain memory address. ESP cannot contain displacement from base ESP address. address. ... See Figure 2.38, page 170. 2004 © Morgan Kaufman Publishers Spring 2014, Jan 24 . . . Spring ELEC 5200-001/6200-001 Lecture 3 49 IA-32 Typical Instructions Four major types of integer instructions: – Data movement including move, push, pop – Arithmetic and logical (destination register or memory) – Control flow (use of condition codes / flags ) – String instructions, including string move and string compare 2004 © Morgan Kaufman Publishers Spring 2014, Jan 24 . . . Spring ELEC 5200-001/6200-001 Lecture 3 50 Some IA-32 Instructions Some PUSH 5-bit opcode, 3-bit register operand 5-b JE | 3-b 4-bit opcode, 4-bit condition, 8-bit jump offset 4-b | 4-b | Spring 2014, Jan 24 . . . 8-b ELEC 5200-001/6200-001 Lecture 3 51 Some IA-32 Instructions Some MOV 6-bit opcode, 8-bit register/mode*, 8-bit offset 6-b |d|w| 8-b | 8-b bit indicates byte or double word operation bit indicates move to or from memory XOR 8-bit opcode, 8-bit reg/mode*, 8-bit base, 8-b index 8-b | 8-b | 8-b | 8-b *8-bit register/mode: See Figure 2.42, page 174. Spring 2014, Jan 24 . . . ELEC 5200-001/6200-001 Lecture 3 52 Some IA-32 Instructions Some ADD 4-bit opcode, 3-bit register, 32-bit immediate 4-b | 3-b |w| TEST 32-b 7-bit opcode, 8-bit reg/mode, 32-bit immediate 7-b Spring 2014, Jan 24 . . . |w| 8-b | ELEC 5200-001/6200-001 Lecture 3 32-b 53 Additional References IA-32, IA-64 (CISC) A. S. Tanenbaum, Structured Computer Organization, Fifth A. Edition, Upper Saddle River, New Jersey: Pearson PrenticeEdition Hall, 2006, C...
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This document was uploaded on 02/23/2014 for the course COMUPER AR 6200 at Auburn University.

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