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This beta has full bypass and annulment logic a 2

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Unformatted text preview: This Beta has full bypass and annulment logic. (A) (2 points) How many fetched instructions are annulled following a BNE instruction when the branch is taken? When the branch is not taken? Annulments when branch taken: __1__; not taken: __0__ Consider the execution of the following sequence in kernel mode on the 5-stage pipelined Beta: A: ADDC(R31, 44, R0) SUBC(R0, 0, R1) MULC(R0, 23, R4) LD(R0, 0, R2) XORC(R2, 1, R3) Although not required, you may find the blank pipeline timing diagram on the back of the previous page useful for scratch purposes. (B) (2 points) Are there points in the execution of the sequence when data is bypassed from the ALU stage back to the RF stage? I...
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This document was uploaded on 02/27/2014 for the course COMSCI 6.004 at MIT.

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