q4solutions

Q4solutions

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ght. As this system uses the Beta, assume byte addressing for both virtual and physical addresses. Gill’s plan is to keep a page map in main memory (RAM), and add a small Translation Lookaside Buffer (TLB) to cache virtual-to-physical page translations. His thinking is that most accesses to virtual memory will result in TLB hits, and misses can simply be handled by a “TLBMiss” handler in the OS kernel. He has modified the Beta data path to splice the virtual-tophysical translation apparatus into the Beta’s data paths, and changed the control logic to generate a TLBMiss exception under appropriate circumstances. Note that when PC[31] is one, Gill’s design selects the low-order m bits of the virtual page number as the physical page. Gill has chosen the following parameters for his implementation: p=14, v=18, m=14. The pagemap is stored in main memory as a simple array of entries, each entry containing a PPN as well as Resident and Dirty bits packed into as few bytes as possible. (A) (1 point): Recall that on reset (startup), the Beta begins execution by fetching the instruction at (virtual) location zero. What is the physical address of the first instruction executed after Gill’s modifications? Give a hex physical address, or “NONE” if you can’t tell from the information given. 0 Physical address of first instruction, or “NONE”: 0x__________ (B) (1 point): How many entries are required for the pagemap? or 80000000 18 2 Number of pagemap entries: __________ (C) (2 points): How many pages of main memory are required to hold the pagemap? What fraction of physical memory is used to hold the pagemap? 5 2 Physical pages to hold pagemap: __________ 5 14 2 /2 = Fraction of physical memory used for pagemap: __________ For simplicity, Gill hasn’t implemented Resident or Dirty bits in the TLB. The TLB is assumed to contain entries only for resident pages, and all resident pages are assumed to be dirty. 6.004 Spring 2010 - 2 of 4 - Quiz #4 1/512 Problem 2 (continued): Gill’s crack software team has implemented the following handler for TLB misses, which has been thoroughly tested and works fine: void TLBMissHandler(int VPN) { if (NonResident(VPN)) PageFault(VPN); else { ppn = PageMap...
View Full Document

This document was uploaded on 02/27/2014 for the course COMSCI 6.004 at MIT.

Ask a homework question - tutors are online