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Regsxp userregsxp 4 tlbmisshandler is called by an

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Unformatted text preview: [VPN]; TLBEnter(vpn, ppn); User.Regs[XP] = User.Regs[XP]-4; } } TLBMissHandler is called by an assembly-language stub when a TLB miss interrupt is taken, and is passed the virtual page number from the memory reference which caused the miss. Note that the handler calls OS kernel procedures NonResident (to determine if a page is resident), PageFault (to handle a page fault), and TLBEnter (to enter a new <VPN/PPN> pair into the TLB). (D) (1 point): Exactly one of the procedures called in the above handler calls Scheduler(). Which is it? circle one: NonResident … PageFault … TLBEnter (E) (1 point): Exactly one of the procedures called in the above handler does not access the pagemap stored in main memory. Which is it? circle one: NonResident … PageFault … TLBEnter (F) (1 point): An application tries to read virtual location 0x100, and the access causes a TLB miss. During which, if any, of the procedure calls does the actual read of virtual location 0x100 happen? circle one: NonResident … PageFault … TLBEnter … NONE Upset by the performance cost of assuming every page to be dirty, Gill has his engineers add a Dirty bit to each TLB entry and hardware to set it on writes. After appropriate software changes are made, Gill finds a substantial improvement in average OS performance. He measures the average time spent in each of the routines called by TLBMissHandler to determine what has changed. (G) (3 points): Which procedures would you expect to take less time (faster) on the average as a result of this change? More time (slower)? circle one: NonResident is FASTER … UNCHANGED … SLOWER circle one: PageFault is FASTER … UNCHANGED … SLOWER circle one: TLBEnter is FASTER … UNCHANGED … SLOWER 6.004 Spring 2010 - 3 of 4 - Quiz #4 Problem 3. (7 points): Caches -- The Big Picture Consider the universe of caches constructed from one or more static RAM lookup tables organized as shown on the right, i.e. as table allowing access to a single entry (line) at a time, each line having a tag portion as well as 2B data entries. Combining multiple of these devices along with necessary logic, comparators, and replacement st...
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This document was uploaded on 02/27/2014 for the course COMSCI 6.004 at MIT.

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