Unformatted text preview: bit to each TLB entry and hardware to set it on writes. After appropriate software changes
are made, Gill finds a substantial improvement in average OS performance. He measures the
average time spent in each of the routines called by TLBMissHandler to determine what has
(G) (3 points): Which procedures would you expect to take less time (faster) on the average
as a result of this change? More time (slower)?
circle one: NonResident is FASTER … UNCHANGED … SLOWER
circle one: PageFault is FASTER … UNCHANGED … SLOWER
circle one: TLBEnter is FASTER … UNCHANGED … SLOWER
6.004 Spring 2010 - 3 of 4 - Quiz #4 Problem 3. (7 points): Caches -- The Big Picture
Consider the universe of caches constructed from one or more static RAM lookup
tables organized as shown on the right, i.e. as table allowing access to a single entry
(line) at a time, each line having a tag portion as well as 2B data entries.
Combining multiple of these devices along with necessary logic, comparators, and
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- Spring '13
- Virtual memory, CPU cache, main memory, virtual page number, Gill Bates, single-digit decimal addresses