q4 (1) Computer Structures

As this system uses the beta assume byte addressing

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Unformatted text preview: s this system uses the Beta, assume byte addressing for both virtual and physical addresses. Gill’s plan is to keep a page map in main memory (RAM), and add a small Translation Lookaside Buffer (TLB) to cache virtual-to-physical page translations. His thinking is that most accesses to virtual memory will result in TLB hits, and misses can simply be handled by a “TLBMiss” handler in the OS kernel. He has modified the Beta data path to splice the virtual-tophysical translation apparatus into the Beta’s data paths, and changed the control logic to generate a TLBMiss exception under appropriate circumstances. Note that when PC[31] is one, Gill’s design selects the low-order m bits of the virtual page number as the physical page. Gill has chosen the following parameters for his implementation: p=14, v=18, m=14. The pagemap is stored in main memory as a simple array of entries, each entry containing a PPN as well as Resident and Dirty bits packed into as few bytes as possible. (A) (1 point): Recall that on reset (startup), the Beta begins execution by fetching the instruction at (virtual) l...
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