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Altera corporation 25 university program design

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Unformatted text preview: onitor while it is receiving color data. Figures 13 and 14 show the timing waveforms for the color information with respect to the horizontal and vertical synchronization signals. Altera Corporation 25 University Program Design Laboratory Package User Guide Figure 13. Horizontal Refresh Cycle RED, GREEN, BLUE 1.89 µs 25.17 µs 0.94 µs HORIZ_SYNC 3.77 µs 31.77 µs Figure 14. Vertical Refresh Cycle 480 Horizontal Refresh Cycles RED, GREEN, BLUE 1.02 ms 15.24 ms 0.35 ms VERT_SYNC 64 µs 16.6 ms The frequency of operation and the number of pixels that the monitor must update determines the time required to update each pixel, and the time required to update the whole screen. The following equations roughly calculate the time required for the monitor to perform all of its functions. 26 Altera Corporation University Program Design Laboratory Package User Guide Tpixel = = 1/fCLK 40 ns TROW = = = = A (Tpixel × 640 pixels)/(row + guard bands) 25 µs + B + C + E 31.77 µs Tscreen = = = (TROW × 480 rows) + guard bands 15.5 ms + P + Q + S 16.6 ms fRR = = 1/TROW 31.5 KHz fSR = = 1/Tscreen 60 Hz Where: Tpixel fCLK TROW Tscreen fRR fSR = = = = = = Time required to update a pixel 25.175 MHz Time required to update one row Time required to update the screen Row refresh frequency Screen refresh frequency The monitor writes to the screen by sending red, green, blue, horizontal sync, and vertical synchronization signals when the screen is at the expected location. Once the timing of the horizontal and vertical synchronization signals is accurate, the monitor only needs to keep track of the current location, so it can send the correct color data to the pixel. MOUSE Interface Operation You can connect a mouse to the UP 1 Education Board via the 6-pin mini-DIN connector. The data is sent using a synchronous serial protocol, and the transmission is controlled by the CLK and DATA signals. During non-transmission, CLK is at logic 1 and DATA can be either logic 0 or logic 1. Each transmission contains one start bit, eight data bits,...
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  • Spring '14
  • Logic gate, Programmable logic device, Design Laboratory Package, Program Design Laboratory, University Program Design, Laboratory Package User

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