An led is illuminated when a logic 0 is applied to

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: oard contains 16 LEDs that are pulled-up with a 330-Ω resistor. An LED is illuminated when a logic 0 is applied to the female header associated with the LED. LEDs D1 through D8 are connected in the same sequence to the female headers (i.e., D1 is connected to position 1, and D2 is connected to position 2). LEDs D9 through D16 are connected in the same sequence to the female headers (i.e., D9 is connected to position 1, and D10 is connected to position 2). See Figure 3. Figure 3. LED Positions Female Header Position 1 2 3 4 5 6 7 8 8 LEDs D1 D5 D2 D6 D3 D7 D4 D8 Female Header Position 1 2 3 4 5 6 7 8 LEDs D9 D13 D10 D14 D11 D15 D12 D16 Altera Corporation University Program Design Laboratory Package User Guide MAX_DIGIT Display MAX_DIGIT is a dual-digit seven-segment display connected directly to the EPM7128S device. Each LED segment of the display can be illuminated by driving the connected EPM7128S device I/O pin with a logic 0. Figure 4 shows the name of each segment. Figure 4. Display Segment Name Digit 1 f Digit 2 a a e b f c g e g b c d d Decimal Point Table 4 lists the pin assignments for each segment. Table 4. MAX_DIGIT Segment I/O Connections Display Segment Pin for Digit 1 Pin for Digit 2 a 58 69 b 60 70 c 61 73 d 63 74 e 64 76 f 65 75 g 67 77 Decimal point 68 79 MAX_EXPANSION MAX_EXPANSION is a dual row of 0.1-inch spaced holes for accessing signal I/O pins and global signals on the EPM7128S device, power, and ground. Figure 5 shows the numbering convention for the holes. Altera Corporation 9 University Program Design Laboratory Package User Guide Figure 5. MAX_EXPANSION Numbering Convention 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 MAX_EXPANSION UP 1 Education Board ® EPM7128S Table 5 lists the signal names and the EPM7128S device pins connected to each hole. Table 5. MAX_EXPANSION Signal Names & Device Connections (Part 1 of 2) Hole Number Signal/Pin Hole Number Signal/Pin 1 RAW 2 GND 3 VCC 4 GND 5 VCC 6 GND 7 No Connect 8 No Connect 9 No Connect 10 No Connect 11 No Connect 12 GCLRn/1 13 OE1/84 14 OE2/GCLK2/2 15 4 16 5 17 6 18 8 19 9 20 10 21 11 22 12 23 15 24 16 25 17 26 18 27 20 28 21 29 22 30 24 31 25 32 27 33 28 34 29 35 10 30 36 31 37 33 38 34 Altera Corporation University Program Design L...
View Full Document

  • Spring '14
  • Logic gate, Programmable logic device, Design Laboratory Package, Program Design Laboratory, University Program Design, Laboratory Package User

{[ snackBarMessage ]}

Ask a homework question - tutors are online