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Unformatted text preview: Cable for Connecting Multiple UP 1 Education Boards Together Attach the ByteBlaster directly to your PC’s parallel port and to the JTAG_IN connector on the UP 1 Education Board. For more information on setting up the ByteBlaster, go to the ByteBlaster Parallel Port Download Cable Data Sheet. Setting the JTAG Options in MAX+PLUS II for Connecting Multiple UP 1 Education Boards Together For information on how to set the JTAG Options in MAX+PLUS II, see “Setting the JTAG Options in MAX+PLUS II for Configuring/Programming Both Devices” on page 22. 24 Altera Corporation University Program Design Laboratory Package User Guide VGA Driver Operation A standard VGA monitor consists of a grid of pixels that can be divided into rows and columns. A VGA monitor typically contains 480 rows, with 640 pixels per row, as shown in Figure 12. Each pixel can display various colors, depending on the state of the red, green, and blue signals. Figure 12. VGA Monitor 640 pixels (0,0) 480 pixels (640, 480) Each VGA monitor has an internal clock that determines when each pixel is updated. This clock operates at the VGA-specified frequency of 25.175 MHz. The monitor refreshes the screen in a prescribed manner that is partially controlled by the horizontal and vertical synchronization signals. The monitor starts each refresh cycle by updating the pixel in the top left-hand corner of the screen, which can be treated as the origin of an X–Y plane (see Figure 12). After the first pixel is refreshed, the monitor refreshes the remaining pixels in the row. When the monitor receives a pulse on the horizontal synchronization, it refreshes the next row of pixels. This process is repeated until the monitor reaches the bottom of the screen. When the monitor reaches the bottom of the screen, the vertical synchronization pulses, causing the monitor to begin refreshing pixels at the top of the screen (i.e., at [0,0]). VGA Timing For the VGA monitor to work properly, it must receive data at specific times with specific pulses. Horizontal and vertical synchronization pulses must occur at specified times to synchronize the m...
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This document was uploaded on 02/25/2014.

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