Start bits are logic 0 and stop bits are logic 1 each

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Unformatted text preview: odd parity, and one stop bit. Data transmission starts from the least significant bit (LSB), i.e., the sequence of transmission is start bit, DATA0 through DATA7, parity, stop bit. Start bits are logic 0, and stop bits are logic 1. Each clock period is 30 to 50 µsec; the data transition to the falling edge of the clock is 5 to 25 µsec. Table 13 shows the data packet format. Altera Corporation 27 University Program Design Laboratory Package User Guide Table 13. Data Packet Format Note (1) Packet Number D7 D6 D5 D4 D3 D2 D1 D0 1 YV XV YS XS 1 0 R L 2 X7 X6 X5 X4 X3 X2 X1 X0 3 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Note: (1) where: L R X0 – X7 Y0 – Y7 XS, YS XV, YV = = = = = = Left button state (1 = left mouse button is pressed down) Right button state (1 = right mouse button is pressed down) Movement in X direction Movement in Y direction Movement data sign (1 = negative) Movement data overflow (1 = overflow has occurred) The mouse operates on a Cartesian coordinate system (i.e., moving to the right is positive, moving to the left is negative, moving up is positive, and moving down is negative). The magnitude of the movement is a function of the mouse’s rate of movement. The faster the mouse moves, the greater the magnitude. ® 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 University Program: [email protected] Literature Services: (888) 3-ALTERA [email protected] 28 Altera, MAX, MAX+PLUS, MAX+PLUS II, MAX 7000S, EPM7128S, FLEX, FLEX 10K, EPF10K20, ByteBlaster, EPC1, and AHDL are trademarks and/or service marks of Altera Corporation in the United States and other countries. Altera acknowledges the trademarks of other organizations for their respective products or services mentioned in this document. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Copyright © 1997 Altera Corporation. All rights reserved. Altera Corporation Printed on Recycled Paper....
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  • Spring '14
  • Logic gate, Programmable logic device, Design Laboratory Package, Program Design Laboratory, University Program Design, Laboratory Package User

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