L15 - 18-447 Lecture 15 A Whirlwind Tour of Modern...

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CMU 18-447 S’08 L15-1 © 2008 J. C. Hoe 18-447 Lecture 15: A Whirlwind Tour of Modern Microarchitectures James C. Hoe Dept of ECE, CMU March 19, 2008 Announcements: Project, project, project, Midterm, midterm, midterm This lecture won’t be covered on the midterm or the final Handouts: The Microarchitecture of Superscalar Processors, Smith and Sohi, Proceedings of IEEE, 12/1995. (on Blackboard) Practice Midterm CMU 18-447 S’08 L15-2 © 2008 J. C. Hoe Performance Factors T wall-clock = T cyc × CPI × No.Instructions cycles-per-instruction max. combinational delay ISA and compilers
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CMU 18-447 S’08 L15-3 © 2008 J. C. Hoe Going after IPC Scalar Pipeline (baseline) Operation Latency = 1 Peak IPC = 1 Instruction-Level Parallelism = 1 IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB instruction stream base cyc 0 1 2 3 4 5 6 7 8 9 10 CMU 18-447 S’08 L15-4 © 2008 J. C. Hoe Superpipelined Machine Superpipelined Execution OL = 1 baseline cycle (M minor cycles) Peak IPC = M per baseline cycle (1 per minor cycle) ILP = M major cycle = M minor cycles minor cycle instruction stream base cyc 0 1 2 3 4 5 6 7 8 9 10 IF ID EX MEM WB IF IF IF IF IF IF IF IF IF IF IF IF IF IF IF IF IF IF IF IF IF IF IF IF
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CMU 18-447 S’08 L15-5 © 2008 J. C. Hoe Superscalar Machines Superscalar (Pipelined) Execution OL = 1 baseline cycles Peak IPC = N per baseline cycle ILP = N IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB instruction stream base cyc 0 1 2 3 4 5 6 7 8 9 10 IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB CMU 18-447 S’08 L15-6 © 2008 J. C. Hoe Superscalar Datapath I-cache Reg File Read PC D-cache ALU ALU Reg File Write 2 X fetch bandwidth 2 X read ports 2 X Logic Can’t always double resources 2 X write ports Pipe A Pipe B ?
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CMU 18-447 S’08 L15-7 © 2008 J. C. Hoe Superscalar and Superpipelined Achieving peak performance on each architecture depends on finding N or M independent instructions per cycle Superscalar Parallelism Operation Latency: 1 Issuing Rate: N Superscalar Degree: N Superpipeline Parallelism Operation Latency: 1 Issuing Rate: M Superpipelined Degree: M instruction stream IF ID MEM WB IF IF IF IF IF IF IF IF IF IF IF IF IF IF IF IF IF IF IF IF IF ID MEM WB IF ID MEM WB IF ID MEM WB IF ID MEM WB IF ID MEM WB IF ID MEM WB vs.
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