L19 - CMU 18-447 S'08 L19-1 2008 J. C. Hoe 18-447 Lecture...

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CMU 18-447 S’08 L19-1 © 2008 J. C. Hoe 18-447 Lecture 19: Memory Hierarchy: Cache Design James C. Hoe Dept of ECE, CMU April 7, 2008 Graded midterms and mid-semester grade index Handouts: Midterm 2 solutions Read Virtual Memory in Contemporary Microprocessors by Jacob and Mudge (on Blackboard) CMU 18-447 S’08 L19-2 © 2008 J. C. Hoe Basic Cache Parameters ± Let M = 2 m be the size of the address space in bytes sample values: 2 32 , 2 64 ± Let G=2 g be the cache access granularity in bytes sample values: 4, 8 ± Let C be the “capacity” of the cache in bytes sample values: 16 KBytes (L1), 1 MByte (L2) ± Let B = 2 b be the “block size” of the cache in bytes sample values: 16 (L1), >64 (L2) ± Let a be the “associativity” of the cache sample values: 1, 2, 4, 5(?),. .. “C/B”
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CMU 18-447 S’08 L19-3 © 2008 J. C. Hoe M=32, a=2, C=1K, B=4, G=2 : Basic Solution data 0 128-lines x 4-bytes data 1 128-lines x 4-bytes tag0 128-l x 23-b v0 x 1-b tag1 128-l x 23-b v1 x 1-b tag PA[31:9] PA[0] b.o. PA[1] idx PA[8:2] 7 idx 7 idx 7 idx 7 idx = tag 23 hit0 = hit1 2-1-mux 2-1-mux b.o. 2-1-mux d hit0 hit1 HIT DATA hit0 hit1 16 CMU 18-447 S’08 L19-4 © 2008 J. C. Hoe Can you play the same trick on the tag SRAMs? The same cache parameters but tune for “narrower” data SRAMs data 0 256-lines x 2-bytes data 1 256-lines x 2-bytes tag0 128-l x 23-b v0 x 1-b tag1 128-l x 23-b v1 x 1-b tag PA[31:9] PA[0] b.o. PA[1] idx PA[8:2] 7 idx 7 idx 8 {idx,bo} 8 {idx,bo} = tag 23 hit0 = hit1 2-1-mux d hit0 hit1 HIT DATA 16 this part is unchanged 16 16
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CMU 18-447 S’08 L19-5 © 2008 J. C. Hoe Can you play the same trick on the tag SRAMs? The same cache parameters but tune for “fatter” data SRAMs data 0 64-lines x 8-bytes data 1 64-lines x 8-bytes tag0 128-l x 23-b v0 x 1-b tag1 128-l x 23-b v1 x 1-b tag PA[31:9] PA[0] b.o. PA[1] idx PA[8:2] 7 idx 7 idx 6 PA[8:3] 6 PA[8:3] = tag 23 hit0 = hit1 4-1-mux 4-1-mux {PA[2],b.o.} 2-1-mux d hit0 hit1 HIT DATA hit0 hit1 16 this part is unchanged CMU 18-447 S’08 L19-6 © 2008 J. C. Hoe The same cache parameters but each block frame is interleaved over the 2 SRAM banks data 0 128-lines x 4-bytes data 1 128-lines x 4-bytes tag0 128-l x 23-b v0 x 1-b tag1 128-l x 23-b v1 x 1-b tag PA[31:9] PA[0] b.o. PA[1] idx PA[8:2] 7 idx 7 idx 7 idx 7 idx = tag 23 h0 = h1 2-1-mux 2-1-mux b.o. 2-1-mux d h0•bo+h1•bo h1•bo+h0•bo HIT DATA h0 h1 16 h0•bo h0•bo h1•bo h1•bo this part is unchanged
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CMU 18-447 S’08 L19-7 © 2008 J. C. Hoe Understanding Cache Misses CMU 18-447 S’08 L19-8 © 2008 J. C. Hoe Classification of Cache Misses ± Compulsory miss (design factor: B and prefetch) ­ first reference to an address (block) always results in a miss ­ subsequent references should hit unless the cache block is displaced for the reasons below dominates when locality is poor ± Capacity miss (design factor: C ) ­ cache is too small to hold everything needed
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This note was uploaded on 04/07/2008 for the course ECE 18447 taught by Professor Hoe during the Spring '08 term at Carnegie Mellon.

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L19 - CMU 18-447 S'08 L19-1 2008 J. C. Hoe 18-447 Lecture...

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