Computer Science 161: Operating Systems Section 7: Virtual Memory CS161 Course Staff [email protected] ~ cs161/ April 7, 2007 1 Introduction Many students say that the VM assignment was their favorite. The tricky bit of this assignment is that it’s hard to test incrementally. This is where design becomes really really important. 2 MIPS r2000/r3000 Review/Overview 2.1 Memory Segments kuseg 0x00000000-0x7fffffff TLB-mapped cacheable user space. Your VM system will deal with this memory. kseg0 0x80000000-0x9fffffff direct-mapped cached kernel space. Pointers in this region—kernel pointers— map directly onto the first 512MB of physical memory. 1
kseg1 0xa0000000-0xbfffffff direct-mapped uncached kernel space: Sys/161 doesn’t emulate the caching properties of the MIPS r3000, but if it did, devices would be mapped into this space. kseg2 0xc0000000-0xffffffff TLB-mapped cacheable kernel space. If you were to swap kernel memory, you could use this—it undergoes the same translations that kuseg undergoes. 3 Your Tasks • Handle TLB faults. • Implement paging – Per-process data structures (page tables) – Global data structures (coremap) – Backing store support – Page eviction algorithms • sbrk() • Performance analysis (we’ll talk about it later) 4 TLB Handling • Take a look at dumbvm for examples. Vahalia pages 419-421 are at the end of this document. • Implement two algorithms—these will both be pretty simple. • We give you TLB Random , TLB Write() , TLB Read() , TLB Probe . TLB Random reserves 8 of the TLB entries; it might be easier to just use TLB Write and random() . • Don’t bother with the address-space id; just clear the whole TLB on every context switch. (Why?) 5 Paging 5.1 Introduction Paging is subtle. You need to manage all the memory mappings for each process, as well as managing the memory of the system. The tricky bits are synchronization.