05 The Microarchitecture Level(1) - The Microarchitecture Level Chapter 4 Outline In this section well learn about Moving data in execution

05 The Microarchitecture Level(1) - The Microarchitecture...

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The Microarchitecture Level Chapter 4
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Outline In this section, we’ll learn about: Moving data in execution Microinstructions Stacks The Java Virtual Machine Pipelining
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The Data Path (1) Figure 4-1. The data path of the example microarchitecture used in this chapter.
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The Data Path (2) Figure 4-2. Useful combinations of ALU signals and the function performed.
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Data Path Timing (1) Figure 4-3. Timing diagram of one data path cycle.
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Data Path Timing (2) Activities of subcycles with subcycle length: The control signals are set up (Δw) The registers are loaded onto the B bus (Δx) The ALU and shifter operate (Δy) The results go along the C bus back to the registers (Δz)
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Memory Operation Figure 4-4. Mapping of the bits in MAR to the address bus.
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Stacks (1) Figure 4-8. Use of a stack for storing local variables. (a) While A is active. (b) After A calls B. (c) After B calls C. (d) After C and B return and A calls D.
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Stacks (2) Figure 4-9. Use of an operand stack for doing an arithmetic computation
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The IJVM Memory Model (1) Defined areas of memory The constant pool The Local variable frame The operand stack The method area
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The IJVM Memory Model (2) Figure 4-10. The various parts of the IJVM memory.
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The IJVM Instruction Set (1) Figure 4-11. The IJVM instruction set. The operands byte , const , and varnum are 1 byte. The operands disp , index , and offset are 2 bytes.
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The IJVM Instruction Set (2) Figure 4-11. The IJVM instruction set. The operands byte , const , and varnum are 1 byte. The operands disp , index , and offset are 2 bytes.
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The IJVM Instruction Set (3) Figure 4-12. (a) Memory before executing INVOKEVIRTUAL.
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  • Winter '14
  • RandyFortier
  • Central processing unit, X86, CPU cache, Branch predictor

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