04 The Digital Logic Level - The Digital Logic Level Chapter 3 Outline In this section well learn about Gates Digital circuits and Boolean logic

# 04 The Digital Logic Level - The Digital Logic Level...

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The Digital Logic Level Chapter 3 Subscribe to view the full document.

Outline In this section, we’ll learn about: Gates Digital circuits and Boolean logic Registers Memory Buses Processor case studies Gates and Boolean Algebra (1) Figure 3-1. (a) A transistor inverter. (b) A NAND gate. (c) A NOR gate. Subscribe to view the full document.

Gates and Boolean Algebra (2) Figure 3-2. The symbols and functional behavior for the five basic gates. Boolean Algebra Figure 3-3. (a) The truth table for the majority function of three variables. (b) A circuit for (a). (b) Subscribe to view the full document.

Implementation of Boolean Functions Write truth table for function Provide inverters to generate complement of each input Draw AND gate for each term with 1 in result column Wire AND gates to appropriate inputs Feed output of all AND gates into an OR gate Circuit Equivalence (1) Figure 3-4. Construction of (a) NOT, (b) AND, and (c) OR gates using only NAND gates or only NOR gates. Subscribe to view the full document.

Circuit Equivalence (2) Figure 3-5. Two equivalent functions. (a) AB + AC Circuit Equivalence (3) Figure 3-5. Two equivalent functions. (b) A(B + C). Subscribe to view the full document.

Circuit Equivalence (4) Figure 3-6. Some identities of Boolean algebra. Circuit Equivalence (5) Figure 3-7. Alternative symbols for some gates: (a) NAND (b) NOR (c) AND (d) OR Subscribe to view the full document.

Circuit Equivalence (6) Figure 3-8. (a) The truth table for the XOR function. (b)–(d) Three circuits for computing it. Circuit Equivalence (7) Figure 3-9. (a) Electrical characteristics of a device. (b) Positive logic. (c) Negative logic. Subscribe to view the full document.

Integrated Circuits Figure 3-10. Common types of integrated-circuit packages, including a dual-inline package (a), pin grid array (b), and land grid array (c). Multiplexers (1) Figure 3-11. An eight-input multiplexer circuit. Subscribe to view the full document.

Multiplexers (2) Figure 3-12. (a) An eight-input multiplexer. (b) The same multiplexer wired to compute the majority function. Decoders Figure 3-13. A 3-to-8 decoder circuit. Subscribe to view the full document.

Comparators Figure 3-14. A simple 4-bit comparator. Arithmetic Circuits (1) Figure 3-15. A 1-bit left/right shifter. Subscribe to view the full document.

Arithmetic Circuits (2) Figure 3-16. (a) Truth table for 1-bit addition.  • Winter '14
• RandyFortier
• Logic gate, PCI Express, Memory Organization

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