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Unformatted text preview: ts. For simplicity, assume there is no time lag in the output response. Keep in mind that
changes in state for this kind of latch occur in response to 0 rather than 1.
Solution: S Q Q R 1
0 Q 1
unde ned 0 Q 1
unde ned 0
time 1 2. A sequential circuit with two D ﬂip-ﬂops A and B , two inputs X and Y , and one output Z is speciﬁed by the
following input equations:
DA = X · A + X · Y , DB = X · B + X · A, (a) Draw the logic diagram of the circuit.
(b) Derive the state table.
(c) Derive the state diag...
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This document was uploaded on 03/01/2014 for the course ECE 25 at UCSD.
- Fall '08