Homework 5 Solutions

For simplicity assume there is no time lag in the

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ts. For simplicity, assume there is no time lag in the output response. Keep in mind that changes in state for this kind of latch occur in response to 0 rather than 1. Solution: S Q Q R 1 S 0 R 1 0 Q 1 unde ned 0 Q 1 unde ned 0 time 1 2. A sequential circuit with two D flip-flops A and B , two inputs X and Y , and one output Z is specified by the following input equations: DA = X · A + X · Y , DB = X · B + X · A, (a) Draw the logic diagram of the circuit. (b) Derive the state table. (c) Derive the state diag...
View Full Document

This document was uploaded on 03/01/2014 for the course ECE 25 at UCSD.

Ask a homework question - tutors are online