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Unformatted text preview: - 2. (15 points) The following questions relate to memories.
(a) (5 points) The following illustrates the timing parameters for an SRAM: Consider a situation in which OE_L and CS_L are initially deasserted, and then at the
same time, OE_L is asserted, CS_L is asserted, and a new address appears on the ADDR
lines. If tOE = 1.5ns, tAA = 2ns, and tACS = 2.5ns, when does the data from the new
address appear on DOUT? (b) (5 points) Consider a 64x1 DRAM (holds 64 bits and has one data input/output). How
many address lines are needed? 5 ECE 2300: Introduction to Digital Logic Design
NET ID: ___________ Spring 2010 (c) (5 points) Consider a ROM that implements four logic functions that use the same six
variables as inputs. How many data inputs and data outputs are required? 3. (25 points) Consider the single cycle processor discussed in class: (a) (20 points) Fill in the following fields. Assume eight registers. An offset or immediate
value, if required for a particular instruction, is incorporated into the IMM/OFF field. Fo...
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This test prep was uploaded on 03/02/2014 for the course ECE 2300 taught by Professor Long during the Spring '08 term at Cornell University (Engineering School).
- Spring '08
- Computer Architecture