# C 7 points draw the state diagram make sure to

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Unformatted text preview: ent state). (c) (7 points) Draw the state diagram. Make sure to completely label all transitions. Explain the operation of the circuit. 3 ECE 2300: Introduction to Digital Logic Design NET ID: ___________ Spring 2010 (d) (10 points) Based on your state diagram in (c), fill in the code for the always block that generates the values of the next state (Snext). input Clock,In; output Out; reg [1:0] Sreg, Snext; parameter [1:0] S0 = 2’b00, //state values S1 = 2’b01, S2 = 2’b10, S3 = 2’b11; always @ ( begin case ( ) ) endcase end (e) (5 points) Does Q1* have a static-1 hazard? Prove your answer using a KMap. 4 ECE 2300: Introduction to Digital Logic Design NET ID: ___________ Spring 2010 (f) (5 points) Calculate the minimum clock period (minimum time between rising clock edges) of the FSM under the following assumptions: In is driven by a D FF. Out is driven to a D FF. The clock arrives to all D FFs at the same time (zero clock skew). The circuit components have the following propagation delays: Component D FF Inverter 2-input gate 3-input gate Max Propagation Delay 2 3 4 5 Setup Time Hold Time 2 - 1...
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## This test prep was uploaded on 03/02/2014 for the course ECE 2300 taught by Professor Long during the Spring '08 term at Cornell University (Engineering School).

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