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Unformatted text preview: 000 0000000000000000000000000000 00000000000000000 000000000000000000 00000000000000000 000000000000000000 00000000000000000 000000000000000000 00000000000000000 000000000000000000 00000000000000000 000000000000000000 00000000000000000 000000000000000000 00000000000000000 000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000 0000 00000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000 000000000000000000 0000000 00000 00000000000000000000 00000000000000000000 000000000000000000 000000 0000000 p+ n+ n+ p+ p+ 0000 0000 0000 0000 M etal Metal Thick field oxide n+ n well p substrate 82.4 ECEN 475 14 Layout Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain Set by minimum width of polysilicon Feature size improves 30% every 3 years or so Express rules in terms of λ = f/2 E.g. λ = 0.3 µm in 0.6 µm process ECEN 475 92.4 Simplified Design Rules Conservative rules to get you started 03.4 ECEN 475 15 Inverter Layout Transistor dimensions specified as Width / Length Minimum size is 4λ / 2λ, sometimes...
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