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Unformatted text preview: 00000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000 00000000000000000000000000000000 00000000000000000000 p+ n+ n+ p+ p+ n+ n well p substrate substrate tap well tap ECEN 475 9.4 Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line 000000000000000000000000000000000000000 000000000000000000000000000000000000000 A 000000000000000000000000000000000000000 000000000000000000000000000000000000000 000000000000000000000000000000000000000 000000000000000000000000000000000000000 000000000000000000000000000000000000000 000000000000000000000000000000000000000 000000000000000000000000000000000000000 000000000000000000000000000000000000000 000000000000000000000000000000000000000 000000000000000000000000000000000000000 000000000000000000000000000000000000000 Y 000000000000000000000000000000000000000 000000000000000000000000000000000000000 000000000000000000000000000000000000000 000000000000000000000000000000000000000 000000000000000000000000000000000000000 000000000000000000000000000000000000000 000000000000000000000000000000000000000 nMOS transistor substrate tap ECEN 475 VDD pMOS transistor well tap 01.4 GND 5 Detailed Mask Views Six masks n-well Polysilicon n+ diffusion p...
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This document was uploaded on 03/02/2014.

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