G 03 m in 06 m process ecen 475 924 simplified design

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Unformatted text preview: called 1 unit In f = 0.6 µm process, this is 1.2 µm wide, 0.6 µm long ECEN 475 13.4 Gate Layout Layout design can be very time consuming Design gates to fit together nicely Build a library of standard cells Standard cell design methodology VDD and GND should abut (standard height) Adjacent gates should satisfy design rules nMOS at bottom and pMOS at top All gates include well and substrate contacts 23.4 ECEN 475 16 Example: Inverter ECEN 475 33.4 Example: NAND3 Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 VDD rail at top Metal1 GND rail at bottom 32 λ by 40 λ 43.4 ECEN 475 17 Stick Diagrams Stick diagrams help plan layout quickly Need not be in scale Draw with color pencils or dry-erase markers ECEN 475 53.4 Example: O3AI Sketch a stick diagram for O3AI and estimate area Y= (A+B+C)•D 63.4 ECEN 475 18 Example: O3AI Sketch a stick diagram for O3AI and estimate area Y= (A+B+C)•D ECEN 475 73.4 Photolithography 83.4 ECEN 475 19 Reticle Pattern Transfer to Resist UV light source Shutter Alignment laser Shutter is closed...
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This document was uploaded on 03/02/2014.

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