Bandwidth for High Speed Networks

However if viable this all core design would allow

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Unformatted text preview: ile our initial simulations with large latencies did not reveal any signi cant problems, we do not yet understand CSFQ well enough to be con dent in the viability of this all-core" design. However, if viable, this all-core" design would allow all interior routers to have only very simple forwarding and dropping mechanisms, without any need to classify packets into ows. In addition, we should note that it is possible to use a CSFQ-like architecture to provide service guarantees. A possible approach would be to use the route pinning mechanisms described in 23 , and to shape the aggregate guaranteed tra c at each output link of core routers 6 . One of the initial assumptions of this paper was that the more traditional mechanisms used to achieve fair allocations, such as Fair Queueing or FRED, were too complex to implement cost-e ectively at su ciently high speeds. If this is the case, then a more scalable approach like CSFQ is necessary to achieve fair allocations. The CSFQ islands would be comprised of high-speed backbones, and the edge routers would be at lower speeds where classi cation and other per- ow operations were not a problem. However, CSFQ may still play a role even if router technology advances to the stage where the more traditional mechanisms can reach su ciently high speeds. Because the core-version of CSFQ could presumably be retro t on a sizable fraction of the installed router base since its complexity is roughly comparable to RED and can be implemented in software, it may be that CSFQ islands are not high-speed backbones but rather are comprised of legacy routers. Lastly, we should note that the CSFQ approach requires some con guration, with edge routers distinguished from core routers. Moreover, CSFQ must be adopted an island at a time rather than router-by-router. We do not know if this presents a serious impediment to CSFQ's adoption. References 1 J.C.R. Bennett, D.C. Stephens, and H. Zhang. High speed, scalable, and accurate implementation of...
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