lec5-nonideal_jae - Ref W&H Ch 2.4 Lecture 5 Nonideal Transistor Theory 1 Outline Nonideal Transistor Behavior \u2013 High Field Effects \u2022 Mobility

# lec5-nonideal_jae - Ref W&H Ch 2.4 Lecture 5 Nonideal...

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Lecture 5: Nonideal Transistor Theory Ref: W&H Ch 2.4 1
2 Outline Nonideal Transistor Behavior High Field Effects Mobility Degradation Velocity Saturation Channel Length Modulation Threshold Voltage Effects Body Effect Drain-Induced Barrier Lowering Short Channel Effect Leakage Subthreshold Leakage Gate Leakage Junction Leakage Process and Environmental Variations
3 Ideal Transistor I-V Shockley long-channel transistor models 2 cutoff linear saturatio 0 2 2 n gs t ds ds gs t ds ds dsat gs t ds dsat V V V I V V V V V V V V V
4 1 st vs. 2 nd Order nMOS I-V 65 nm IBM process, V DD = 1.0 V
5 2 nd Order Current Model I on = I ds @ V gs = V ds = V DD Saturation I off = I ds @ V gs = 0, V ds = V DD Cutoff
Subthreshold Leakage 6
7 DIBL Electric field from drain affects channel More pronounced in small transistors where the drain is closer to the channel Drain-Induced Barrier Lowering Drain voltage also affects V t High drain voltage causes current to increase . ~ 0.1 ttds VVV  t t ds V V V
DIBL 8
9 Leakage What about current in cutoff? Simulated results What differs? Current doesn’t go to 0 in cutoff Implications: 1) output < VDD 2) static power 3) memory forgets
10 Gate-Induced Drain Leakage Occurs at overlap between gate and drain largest when drain = V DD , gate < 0 Thwarts efforts to reduce subthreshold leakage with gate voltage < 0, but also impacts gate = 0
11 Subthreshold Leakage Subthreshold leakage exponential with V gs n is process dependent typically 1.3-1.7 Rewrite relative to I off on log scale S ≈ 100 mV/decade @ room temperature 0 0 e 1 e gs t ds sb ds T T V V V k V V nv v ds ds I I
DIBL 12
FINFET DIBL First finFETs were manufactured on an insulating layer. Current can't flow "underneath" the gate when the transistor is OFF ==> reduced leakage. Later techniques for reducing leakage current from flowing in the bulk ==> allowed Bulk finFETs. High doping gradients along the height of the fin prevent current from flowing in the bulk.