Lecture 6:
DC & Transient Response
1
2
Outline
Pass Transistors
DC Response
Logic Levels and Noise Margins
Transient Response
RC Delay Models
Delay Estimation
3
Pass Transistors
We have assumed source is grounded
What if source > 0?
(Which side is S?)
–
e.g. pass transistor passing V
DD
V
g
= V
DD
–
If V
s
> V
DD
V
t
, V
gs
< V
t
–
Hence transistor would turn itself off
nMOS pass transistors pull no higher than V
DD
V
tn
–
Called a degraded “1”
(See Prob. 2.14 – noninv)
–
Approach degraded value slowly (low I
ds
)
pMOS pass transistors pull no lower than V
tp
Transmission gates are needed to pass both 0 and 1
V
DD
V
DD
4
Pass Transistor Ckts
Output = S (why)?
5
DC Response
DC Response: V
out
vs. V
in
for a gate
(SPICE model)
Ex: Inverter
(Vout swings rail to rail)
– V
in
= 0
>
V
out
= V
DD
– V
in
= V
DD
>
V
out
= 0
–
In between, V
out
depends on
transistor size and current
–
By KCL, must settle such that
I
dsn
= I
dsp

(current in = current out)
–
We could solve equations
–
But graphical solution gives more insight
I
dsn
I
dsp
V
out
V
DD
V
in
6
Transistor Operation
Current depends on region of transistor behavior
For what V
in
and V
out
are nMOS and pMOS in
–
Cutoff?
–
Linear?
–
Saturation?
7
nMOS Operation
Cutoff
Linear
Saturated
V
gsn
< V
tn
V
in
< V
tn
V
gsn
> V
tn
V
in
> V
tn
V
dsn
< V
gsn
– V
tn
V
out
< V
in
 V
tn
V
gsn
> V
tn
V
in
> V
tn
V
dsn
> V
gsn
– V
tn
V
out
> V
in
 V
tn
I
dsn
I
dsp
V
out
V
DD
V
in
V
gsn
= V
in
V
dsn
= V
out
8
pMOS Operation
Cutoff
Linear
Saturated
V
gsp
> V
tp
V
in
> V
DD
+ V
tp
V
gsp
< V
tp
V
in
< V
DD
+ V
tp
V
dsp
> V
gsp
– V
tp
V
out
> V
in
 V
tp
V
gsp
< V
tp
V
in
< V
DD
+ V
tp
V
dsp
< V
gsp
– V
tp
V
out
< V
in
 V
tp
I
dsn
I
dsp
V
out
V
DD
V
in
V
gsp
= V
in
 V
DD
V
dsp
= V
out
 V
DD
V
tp
< 0
9
IV Characteristics
Vgs(n)=Vdd*n/5
Make pMOS is wider than nMOS such that
n
=
p
10
Current vs. V
out
, V
in
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
,
I
dsp

V
out
V
DD
11
Load Line Analysis
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
,
I
dsp

V
out
V
DD
For a given V
in
:
–
Plot I
dsn
, I
dsp
vs. V
out
– V
out
must be where currents are equal in
I
dsn
I
dsp
V
out
V
DD
V
in
12
Load Line Analysis
V
in
= 0
V
in5
V
in4
V
in3
V
in2
V