3Pass TransistorsWe have assumed source is groundedWhat if source > 0? (Which side is S?)–e.g. pass transistor passing VDDVg= VDD–If Vs> VDD-Vt, Vgs< Vt–Hence transistor would turn itself offnMOS pass transistors pull no higher than VDD-Vtn–Called a degraded “1” (See Prob. 2.14 – noninv)–Approach degraded value slowly (low Ids)pMOS pass transistors pull no lower than VtpTransmission gates are needed to pass both 0 and 1VDDVDD
4Pass Transistor CktsOutput = S (why)?
5DC ResponseDC Response: Voutvs. Vinfor a gate (SPICE model)Ex: Inverter (Vout swings rail to rail)– Vin= 0 -> Vout= VDD– Vin= VDD-> Vout= 0–In between, Voutdepends ontransistor size and current–By KCL, must settle such thatIdsn= |Idsp| (current in = current out)–We could solve equations–But graphical solution gives more insightIdsnIdspVoutVDDVin
6Transistor OperationCurrent depends on region of transistor behaviorFor what Vinand Voutare nMOS and pMOS in–Cutoff?–Linear?–Saturation?